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copyright ? 2015 future technology devices international limited 1 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 future technology devices international ltd. ft81x ( advanced embedded video engine ) t he ft81x is a series of easy to use g raphic c ontroller s targeted at embedded application s to generate high - quality human machine interfaces (hmis) . it has the following features: ? advanced embedded video engine(eve) with high resolution graphics and video playback ? ft81x functionality includes graphic co ntrol , audio control , and touch control interface . ? pin out back ward compatible with ft800 (ft810) and ft801 (ft811) . ? support multiple widget s for simplified design implementation ? built - in graphics operations allow user s with little expertise to create high - quality display s ? support 4 - wire resistive touch screen (ft810/ ft812) ? support capacitive touch screen with up to 5 touches detection (ft811/ft813) ? hardware engine can recognize touch tags and track touch movement. p rovides notification for u p to 255 touch tag s. ? enhanced sketch processing ? programmable i nterrupt c ontrol ler provide s interrupts to host mcu ? built - in 12mhz crystal oscillator with pll provid ing programmable system clock up to 60mhz ? clock switch command for internal or external clock sourc e . external 12mhz crystal or clock input can be used for higher accuracy . ? video rgb parallel output ; c onfigurable to support pclk up to 60 mhz and r/g/b output of 1 to 8 bits ? programmable timing to adjust hsync and vsync timing, enabling interface to numerous displays ? support for lcd display with resolution up to s vga (800x 60 0 ) and formats with data enable (de) mode or vsync/hsync mode ? support landscape and portrait orientations ? display e nable control output to lcd panel ? integrated 1mbyte graphics ram, no frame buffer ram required ? support playback of motion - jpeg encoded a vi videos ? mono audio channel output with pwm output ? built - in s ound synthesi zer ? audio wave playback for mono 8 - bi t l inear pcm, 4 - bit adpcm and - law coding format at sampling frequenc ies from 8khz to 48khz. built - in digital filter reduce s the system desig n complexity of external filter ing ? pwm output for display backlight dimming control ? advanced object oriented architecture enables low cost mpu /mcu as system host using spi i nterfaces ? support spi data lines in single, dual or quad mode ; spi clock up to 30mh z ? power mode control allow s the chip to be put in p ower down, s leep and s tandby states ? s upports i/o voltage from 1. 8 v to 3. 3 v ? internal voltage regulator supplies 1.2 v to the digital core ? build - in power - on - reset circuit ? - 40c to 85c exten ded operating temp erature range ? available in a compact pb - free , v qf n - 48 and vqfn - 56 package , rohs compliant
copyright ? 2015 future technology devices international limited 2 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 disclaimer: neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. this product and its documentation are supplied on an as - is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, dev ice or system in which the failure of the product might reasonably be expected to result in personal injury. this document provides preliminary information that may be subject to change without notice. no freedom to use patents or other intellectual proper ty rights is implied by th e publication of this document. future techn ology devices international ltd uni t 1, 2 seaward place centurion business park glasgow g41 1hh united kingdom scotland registered company number: sc136640
copyright ? 2015 future technology devices international limited 3 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 1 typical applications ? point of sale s machine s ? multi - function printer s ? i nstrumentation ? home security systems ? graphic touch pad C remote, dial pad ? tele / video conference systems ? phones and switchboards ? medical appli ances ? blood pressure displays ? heart monitors ? glucose level displays ? breathalyzers ? gas chromatographs ? power meter ? home appliance devices ? set - top box ? thermostats ? sprinkler system displays ? medical appliances ? gps / satnav ? vending machine control panels ? elevator controls ? and many more 1.1 pa rt numbers part number description package ft810q - x eve with 18 bit rgb, resistive touch 48 pin vqfn , body 7 x 7 mm, pitch 0.5mm ft811q - x eve with 18 bit rgb, capacitive touch 48 pin vqfn , body 7 x 7 mm , pitch 0.5mm ft812q - x eve with 24 bit rgb, resisti ve touch 56 pin vqfn , body 8 x 8 mm , pitch 0.5mm ft813q - x eve with 24 bit rgb, capacitive touch 56 pin vqfn , body 8 x 8 mm , pitch 0.5mm table 1 - ft81x embedded video engine part numbers note: packaging codes for x is: - r: taped and reel ( 3000pcs per reel ) - t: tray packing (26 0 pcs per tray for vqfn - 48, 348 pcs per tray for vqfn - 56 ) for example: ft81 0q - r is 30 00 vqfn pieces in taped and reel packaging
copyright ? 2015 future technology devices international limited 4 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 2 block diagram figure 2 - 1 ft81x block diagram for a description of each function please refer to section 4. figure 2 - 2 ft81x system design diagram ft81x with eve (embedded video engine ) technology simplifies the system architecture for advanced human machine interfaces (hmis) by providing support for display, audio, and touch as w ell as an object oriented architecture approach that extends from display creation to the rendering of the graphics.
copyright ? 2015 future technology devices international limited 5 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 contents 1 typical applications ................................ ................................ ...... 3 1.1 part numbers ................................ ................................ ...................... 3 2 block diagram ................................ ................................ .............. 4 3 device pin out and signal description ................................ .......... 7 3.1 ft810 vqfn - 48 package pin out ................................ ........................ 7 3.2 ft811 vqfn - 48 package pin out ................................ ........................ 7 3.3 ft812 vqfn - 56 pac kage pin out ................................ ........................ 8 3.4 ft813 vqfn - 56 package pin out ................................ ........................ 8 3.5 pin description ................................ ................................ ................... 9 4 function description ................................ ................................ ... 13 4.1 quad spi host interface ................................ ................................ ... 13 4.1.1 qspi interface ................................ ................................ ................................ ........... 13 4.1.2 serial data protocol ................................ ................................ ................................ ... 15 4.1.3 host memory read ................................ ................................ ................................ ..... 15 4.1.4 host memory write ................................ ................................ ................................ .... 16 4.1.5 host command ................................ ................................ ................................ .......... 16 4.1.6 interrupts ................................ ................................ ................................ ................. 20 4.2 system clock ................................ ................................ .................... 20 4.2.1 clock source ................................ ................................ ................................ ............. 20 4.2.2 phase locked loop ................................ ................................ ................................ ..... 21 4.2.3 clock enable ................................ ................................ ................................ ............. 21 4.2.4 clock frequency ................................ ................................ ................................ ........ 22 4.3 graphics engine ................................ ................................ ................ 22 4.3.1 introduction ................................ ................................ ................................ .............. 22 4.3.2 rom and ram fonts ................................ ................................ ................................ ... 22 4.4 parallel rgb interface ................................ ................................ ...... 26 4.5 miscellaneo us control ................................ ................................ ....... 28 4.5.1 backlight control pin ................................ ................................ ................................ .. 29 4.5.2 disp control pin ................................ ................................ ................................ ........ 29 4.5.3 general purpose io pins ................................ ................................ ............................. 29 4.5.4 pins drive current control ................................ ................................ .......................... 29 4.6 audio engine ................................ ................................ ..................... 30 4.6.1 sound synthesizer ................................ ................................ ................................ ..... 30 4.6.2 audio playback ................................ ................................ ................................ .......... 32 4.7 touch - screen engine ................................ ................................ ........ 32 4.7.1 resistive touch control ................................ ................................ .............................. 32 4.7.2 capacitive touch control ................................ ................................ ............................ 33 4.7.3 compatibi lity mode ................................ ................................ ................................ .... 34
copyright ? 2015 future technology devices international limited 6 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.7.4 extended mode ................................ ................................ ................................ ......... 34 4.7.5 short - circuit protection ................................ ................................ ............................... 35 4.7.6 capacitive touch configuration ................................ ................................ ..................... 35 4.7.7 touch detection in none - active state ................................ ................................ .......... 35 4.8 power management ................................ ................................ .......... 35 4.8.1 power supply ................................ ................................ ................................ ............. 35 4.8.2 internal regulator and por ................................ ................................ ......................... 36 4.8.3 power modes ................................ ................................ ................................ ............. 37 4.8.4 reset and boot - up sequence ................................ ................................ ....................... 38 4.8.5 pin status at different power states ................................ ................................ ............. 38 5 memory map ................................ ................................ ............... 40 5.1 registers ................................ ................................ .......................... 40 5.2 chip id ................................ ................................ ............................. 45 6 devices characteristics and ratings ................................ ........... 46 6.1 absolute maximum ratings ................................ ............................... 46 6.2 esd and latch - up specifications ................................ ....................... 46 6.3 dc characteristics ................................ ................................ ............. 46 6.4 ac characteristics ................................ ................................ ............. 49 6.4.1 system clock and reset ................................ ................................ ............................... 49 6.4.2 spi interface timing ................................ ................................ ................................ ... 49 6.4.3 rgb interface timing ................................ ................................ ................................ . 50 7 application examples ................................ ................................ . 52 8 package parameters ................................ ................................ ... 54 8.1 vqfn - 48 package dimensions ................................ .......................... 54 8.2 vqfn - 56 package dimensions ................................ .......................... 54 8.3 solder reflow profile ................................ ................................ ........ 55 9 contact information ................................ ................................ ... 56 appendix a C references ................................ ................................ ........... 57 appendix b - list of figures and tables ................................ ..................... 58 appendix c - revision history ................................ ................................ .... 60
copyright ? 2015 future technology devices international limited 7 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 3 device pin out and signal description 3.1 ft810 vqfn - 48 package pin out fi gure 3 - 1 pin configuration ft810 vqfn - 48 (top view) 3.2 ft811 vqfn - 48 package pin out figure 3 - 1 pin configuration ft811 vqfn - 48 (top view)
copyright ? 2015 future technology devices international limited 8 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 3.3 ft812 vqfn - 56 package pin out figure 3 - 1 pin configuratio n ft812 vqfn - 56 (top view) 3.4 ft813 vqfn - 56 package pin out figure 3 - 1 pin configuration ft813 vqfn - 56 (top view)
copyright ? 2015 future technology devices international limited 9 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 3.5 pin description table 3 - 1 ft81x pin description pin number pin name type description ft810 ft811 ft812 ft813 - - 1 1 r1 o bit 1 of red rgb signals p owered from pin vccio2 - - 2 2 r0 o bit 0 of red rgb signals p owered from pin vccio2 1 1 3 3 audio_l o audio pwm out p owered from pin vcc 2 2 4 4 gnd p g round 3 3 5 5 sc k i spi clock input p owered from pin vccio 1 4 4 6 6 miso/ io 1 i/o spi single mode: spi miso output spi dual/ quad mode: spi data line 1 p owered from pin vccio 1 5 5 7 7 mosi/ io 0 i/o spi single mode: spi mosi input spi dual/ quad mode: spi data line 0 p owered from pin vccio1 6 6 8 8 cs_n i spi slave select input p owered from pin vccio1 7 7 9 9 gpio0/ io2 i/o spi single /dual mode: general purpose io 0 spi quad mode: spi data line 2 p owered from pin vccio1 8 8 10 10 gpio1 / io3 i/o spi single /dual mode: general purpose io 1 spi quad mode: spi data line 3 p ow ered from pin vccio1 9 9 11 11 vccio 1 p i/o power supply for host interface pins . support 1.8v, 2.5v or 3.3v. 10 10 12 12 gpio2 i /o general purpose io 2 p owered from pin vccio 1 11 1 1 13 13 int_n od / o i nterrupt to host , open drain output (default) or push - pull output , active low 12 12 14 14 pd_n i chip p ower down mode control i nput, active low . connect to mcu gpio for power management or hardware reset function, or pull ed up to vccio 1 through 47 k resistor and 100nf to ground. p owered from pin vccio 1 - - 15 15 gpio3 i / o general purpose io 3 p owered from pin vcc io1
copyright ? 2015 future technology devices international limited 10 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 pin number pin name type description ft810 ft811 ft812 ft813 13 13 16 16 x1/ clk i crystal oscillator or clock input; connect to gnd if not used. 3.3v peak input allowed. p owered fr om pin vcc. 14 14 17 17 x2 o crystal oscillator output; leave open if not used. p owered from pin vcc. 15 15 18 18 gnd p ground 16 16 19 19 vcc p 3.3v power supply input. 17 17 20 20 vout1v2 o 1.2v regulator output pin. connect a 4.7uf decoupling capacitor to gnd. 18 18 2 1 2 1 vcc p 3.3v power supply input. 22 22 vccio 2 p i/o power supply for rgb and touch pins. for qfn - 48 package, vccio2 is bonded together with vcc pin; for qfn - 56 package, vccio2 is separate from vcc pin . vccio2 suppor t s 1.8v, 2.5v or 3.3v. vccio2 can be connected to different voltage with vccio1. 19 23 xp ai / o connect to x right electrode of 4 - wire resistive t o uch - screen panel. p owered from pin vccio2 . 20 2 4 yp ai / o connect to y top electrode of 4 - wire resistive t ouch - screen panel. p owered from pin vccio2 . 21 2 5 xm ai / o connect to x left electrode of 4 - wire resistive t ouch - screen panel. p ow ered from pin vccio2 . 22 2 6 ym ai / o connect to y bottom electrode of 4 - wire resistive t ouch - screen panel. p owered from pin vccio2 . - 19 - 23 ctp_rst_n o connect to reset pin of the ctpm. p owered from pin vccio2. - 20 - 2 4 ctp_ int_n i connect to interrupt pin of the ctpm. p owered from pin vccio2. - 21 - 2 5 ctp_scl i/od connect to i2c scl pin of the ctpm. p owered from pin vccio2. - 22 - 2 6 ctp_sda i/od connect to i2c sda pin of the ctpm. p owered from pin vccio2. 23 23 27 27 gnd p ground 24 24 28 28 backlight o led backlight brightness pwm control signal .
copyright ? 2015 future technology devices international limited 11 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 pin number pin name type description ft810 ft811 ft812 ft813 p owered from pin vccio2. 25 25 29 29 de o lcd data enable . p owered from pi n vccio2. 26 26 30 30 vsync o lcd vertical sync . p owered from pin vccio2. 27 27 31 31 hsync o lcd horizontal sync. p owered from pin vccio2. 28 28 32 32 disp o lcd display enable . p owered from pin vccio2. 29 29 33 33 pclk o lcd pixel clock . p owered from pin vccio2. 30 30 34 34 b7 o bit 7 of blue rgb signals . p owered from pin vccio2. 31 31 35 35 b6 o bit 6 of blue rgb signals . p owered from pin vccio2. 32 32 36 36 b5 o bit 5 of blue rgb sign als . p owered from pin vccio2. 33 33 37 37 b4 o bit 4 of blue rgb signals . p owered from pin vccio2. 34 34 38 38 b3 o bit 3 of blue rgb signals . p owered from pin vccio2. 35 35 39 39 b2 o bit 2 of blue rgb signals . p owered from pin vcci o2. - - 40 40 b1 o bit 1 of blue rgb signals . p owered from pin vccio2. - - 41 41 b0 o bit 0 of blue rgb signals . p owered from pin vccio2. 36 36 42 42 gnd p ground 37 37 43 43 g7 o bit 7 of green rgb signals . p owered from pin vccio2. 38 38 44 44 g6 o bit 6 of green rgb signals . p owered from pin vccio2. 39 39 45 45 g5 o bit 5 of green rgb signals . p owered from pin vccio2. 40 40 46 46 g4 o bit 4 of green rgb signals . p owered from pin vccio2. 41 41 47 47 g3 o bit 3 of gree n rgb signals . p owered from pin vccio2.
copyright ? 2015 future technology devices international limited 12 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 pin number pin name type description ft810 ft811 ft812 ft813 42 42 48 48 g2 o bit 2 of green rgb signals . p owered from pin vccio2. - - 49 49 g1 o bit 1 of green rgb signals . p owered from pin vccio2. - - 50 50 g0 o bit 0 of green rgb signals . p owered from pin vccio2. 43 43 51 51 r7 o bit 7 of red rgb signals . p owered from pin vccio2. 44 44 52 52 r6 o bit 6 of red rgb signals . p owered from pin vccio2. 45 45 53 53 r5 o bit 5 of red rgb signals . p owered from pin vccio2. 46 46 54 54 r4 o bit 4 of red rgb signals . p owered from pin vccio2. 47 47 55 55 r3 o bit 3 of red rgb signals . p owered from pin vccio2. 48 48 56 56 r2 o bit 2 of red rgb signals . p owered from pin vccio2. ep ep ep ep gnd p ground. exposed thermal pad. note: p : power or ground i : input o : output od : open drain output i/ o : bi - direction input and output ai/o: analog input and output
copyright ? 2015 future technology devices international limited 13 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4 function description the ft81x is a single chip , embedded video controller with the following function blocks : ? quad spi host interface ? system clock ? graphics engine ? parallel rgb video interface ? audio engine ? touch - screen support and interface ? power management the functions for each block are briefly described in the following subsections. 4.1 quad spi host interface the ft81x uses a quad serial parallel interface (qspi) to communicate with host microcontrollers and microprocessors . 4.1.1 q spi i nterface the q spi slave interface operates up to 30mhz. only spi mode 0 is supported. refer to section 6.4.2 for detailed timing specification. the qspi can be configured as a spi slave in single , dual or quad channel mode s . by default the spi slave operates in the single channel mode with mosi as input from the master and m iso as output to the master. dual and quad channel modes can be configured through the spi slave itself. to change the channel modes, write to register reg_spi_width. the table below depicts the setting. table 4 - 1 qspi channel selection reg_spi_width[1:0] channel mode data pins max bus speed 00 single C default mode miso, mosi 30 mhz 01 dual io0, io1 30 mhz 10 quad io0, io1, io2, io3 25 mhz 11 reserved - - with dual/quad channel modes, the spi data ports are now unidirectional. in these modes, each spi transaction (signified by cs_n going active low) will begin with the data ports set as inputs. hence, for writ ing to the ft81x , the protocol will operate as in ft800, with wr - command/addr2, addr1, addr 0, datax, datay, dataz the write operation is considered complete when cs_n goes inactive high. for read ing from the ft81x , the protocol will still operate as in ft800, with rd - command/addr2, addr1, addr0, dummy - byte, datax, datay, dataz. however as the data ports are now unidirectional, a change of port direction will occur before datax is clocked out of the ft81x . therefore it is important that the firmware controlling the spi master changes the spi master data port direction to input aft er transmitting addr0. the ft81x will not change the port direction till it starts to clock out datax. hence, the dummy - byte cycles will be used as a change - over period when neither the spi master nor slave will be driving the bus; the data paths thus must have pull - ups/pull - downs. the spi slave from the ft81x will reset all its data ports direction to input once cs_n goes inactive high (i.e. at the end of the current spi master transaction). the diagram depicts the behaviour of both the spi mast er and slave in the master read case.
copyright ? 2015 future technology devices international limited 14 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 4 - 1 spi master and slave in the master read case in the dual channel mode, miso (msb) and mosi are used while in the quad channel mode. io3 (msb), io2, miso and mosi are used. figure 4 - 2 illustrates a direct connection to a 1.8 - 3.3v io mpu/mcu with single or dual spi interface. figure 4 - 3 illustrates a direct connection to a 1.8 - 3.3v io mpu/mcu with quad spi interface. figure 4 - 2 single /dual spi interface conne ction spi master drives the data bus ss wr / addr2 addr 1 addr 2 dum my data x data y data 0 spi slave drives the data bus bus not driven spi master changes data ports in to inputs spi slave changes data ports into outputs spi slave resets data ports into inputs gnd gnd ss# miso mosi sclk pd# int# cs_n miso /io 1 mosi /io 0 sck pd_n int_n ft81x 1.8 - 3.3v vccio1 3.3v vcc 4.7k mpu/mcu
copyright ? 2015 future technology devices international limited 15 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 4 - 3 quad spi interfac e connection 4.1.2 serial d ata p rotocol the ft81x appears to the host mpu /mcu as a memory - mapped spi device. the host com municates with the ft81x using reads and writes to a large ( 4 megabyte) address space. within this address space are dedicated areas for graphics, audio and touch control. refer to section 5 for the detaile d memory map . the host reads and writes the ft81x address space using spi transactions. the se transactions are memory read , memory write and command write . serial data is sent by the most significant bit first. e ach transaction starts with cs_n goes low, and ends when cs_n goes high. theres no limit on data length within one transaction, as long as the memory address is continuous. 4.1.3 host memory read for spi memory read transaction s , t he host sends two zero bit s , followed by the 2 2 - bit address. this is followed by a dummy byte . after the dummy byte, the ft81x responds to each host byte with read data bytes. table 4 - 2 host memory read transaction byte n 7 6 5 4 3 2 1 0 0 0 address [2 1 :16] address [15:8] address [7:0] d ummy byte byte 0 gnd gnd sclk miso io2 ss# pd# int# sck io 1 io2 cs_n pd_n int_n ft81x 1.8 - 3.3v vccio1 3.3v vcc 4.7k mpu/mcu mosi io3 io 0 io3 read data write address
copyright ? 2015 future technology devices international limited 16 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.1.4 host memory write for spi memory write transaction s , the host sends a 1 bit and 0 bit, followed by the 22 - bit address. this is followed by the write da ta. table 4 - 3 host memory write transaction byte n 4.1.5 host command when se nding a command , th e host transmit s a 3 byte command . table 4 - 5 h ost c ommand list s all the host command functions . for spi command transaction s , the host sends a 0 bit and 1 bit, followed by the 6 - bit command code. the 2 nd byte can be either 00h, or the parameter of that command. the 3 rd byte is fixed at 00h . all spi comman ds except the system reset can only be executed when the spi is in the single channel mode. they will be ignored when the spi is in either dual or quad channel mode. some commands are used to configure the device and these configurations will be reset up on receiving the spi p w rdown command, except those that configure the pin state during power down. the se commands will be sticky unless reconfigured or power - on - reset (por) occurs. table 4 - 4 host comma nd transaction 1 st byte 2 nd byte 3 rd byte table 4 - 5 h ost c ommand list 1 st byte 2 nd byte 3 rd byte command description power modes 00000000 b 00000000 b 00000000 b 00 h active switch from standby/sleep /pwrdown modes to active mode . d ummy memory read from address 0 (read twice) generate s active command . 7 6 5 4 3 2 1 0 1 0 address [21:16] address [15:8] address [7:0] byte 0 7 6 5 4 3 2 1 0 0 1 command [5:0] parameter for the command 0 0 0 0 0 0 0 0 write data write address
copyright ? 2015 future technology devices international limited 17 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 1 st byte 2 nd byte 3 rd byte command description 01000001 b 0000000 0 b 00000000 b 4 1 h standby put ft81x core to standby mode. clock gate off, pll and oscillator remain on (default) . active command to wake up. 01000010 b 00000000 b 00000000 b 4 2 h sleep put ft81x core to sleep mode. clock gate off, pll and oscillator off. active command to wake up. 0100 00 11b 01010000 b 00000000 b 00000000 b 43h /50h pwrdown switch off 1.2v core voltage to the digital core circuits . clock, pll and oscillator off. spi is alive. active command to wake up. 01 0 001 00 b xx 00000000b 49h pd _ roms select power down individual roms ; byte2 determines which rom to power down or up. a 1 on a bit powers down the corresponding block; a 0 on a bit powers up the corresponding block. as these are not readable, the host must remember the setting on its own. byte2 [7] rom _main byte2 [6] rom _rcos atan byte2 [5] rom _ sample byte2 [4] rom _ j a boot byte2 [3] rom _ j 1 boot byte2 [ 2 - 0 ] reserved clock and reset 01 0 001 00 b 00000000 b 00000000b 44h clkext select pll input from external crystal oscillator or external input clock . no effect if external clock is al ready selected, otherwise a system reset will be generated 0 1 0 0 1000 b 00000000 b 00000000b 48h clkint select pll input from internal relaxation oscillator (default) . no effect if internal clock is already selected, otherwise a system reset will be generated 01 100001b 01 100010b xx 00000000b 61h/ 6 2h clksel this command will only be effective when the pll is stopped (sleep mode). for compatibility to ft800/ft801 , set byte2 to 0x00. this will set the pll clock back to default (60 mhz) . byte2 [5 :0] sets the clock frequency 0 set to default clock speed 1 reserved 2 to 5 2 to 5 times the osc frequency (i.e. 24 to 60 mhz with 12mhz osc illator )
copyright ? 2015 future technology devices international limited 18 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 1 st byte 2 nd byte 3 rd byte command description byte2 [ 7:6] sets the pll range 0 when byte2[5:0] = 0, 2, 3 1 when byte2[5:0] = 4, 5 01 101000b 00000000 b 00000000b 68h rst _pulse send reset pulse to ft81x core. the behaviour is the same as por except that settings done through spi commands will not be affected co nfiguration 01 110000b xx 00000000b 70h p in drive this will set the drive strength for various pin s. for ft800/ft801 compatibility, by default those settings are from the gpio registers. ft81x supports setting the drive strength via spi command in stead. when pin drive for a pin from the spi command is not updated, the drive strength will be determined by its corresponding gpio register bits, if they exist. if they dont
copyright ? 2015 future technology devices international limited 19 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 1 st byte 2 nd byte 3 rd byte command description 04 - 07 h reserved 08 h disp 09 h de 0a h vsyn c / hsync 0b h pclk 0c h backlight 0d h r [7:0], g [7:0], b [7:0] 0e h audio_l 0f h int_n 10 h ctp_rst_n 11 h ctp_ scl 12 h ctp_ sda 13 h spi miso/mosi/io2/io3 others reserved note : gpio0 shares the same pin as spi io2 and gpio1 with spi io3. when spi is set in quad mode, io2 and io3 will inherit t he drive strength set in group 13 h ; otherwise gpio0 and gpio1 will inherit the drive strength from group 00h and 01h respectively. 01 110001b xx 00000000b 71h pin _pd_sta te during power down, all output and in / out pin s will not be driven. please refer to table 4 - 20 for their default power down state. these settings will only be effective during power down and will not affect normal operations. also note t hat these configuration bits are sticky and, unlike other configuration bits, will not reset to default values upon exiting power down. only por will reset them. byte2 determines which pin and the setting are to be updated. byte2[1:0] determine the pi n state. byte2 [1:0] pin setting 0h float 1h pull - down
copyright ? 2015 future technology devices international limited 20 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 1 st byte 2 nd byte 3 rd byte command description 2h pull - up 3h reserved byte2[7:2] determine which pin / pin group to set. please refer to the table in command pin drive entry. note: any command code not specified is reserved and should not be used by the software 4.1.6 interrupts the interrupt output pin is enabled by reg_int_en. when reg_int_en is 0, int_n is tri - state (pulled to high by external pull - up resistor). wh en reg_int_en is 1, int_n is driven low when any of the interrupt flags in reg_int_flags are high, after masking with reg_int_mask. writing a 1 in any bit of reg_int_mask will enable the correspond ing interrupt. each bit in reg_int_flags is set by a corr esponding interrupt source. reg_int_flags is readable by the host at any time, and clears when read. the int_n pin is open - drain (od) output by default. it can be configured to push - pull output by register reg_gpiox. table 4 - 6 interrupt flags bit assignment bit 7 6 5 4 interrupt sources convcomplete cmdflag cmdempty playback conditions touch - screen conversions completed command fifo flag comm and fifo empty audio playback ended bit 3 2 1 0 interrupt sources sound tag touch swap conditions sound effect ended touch - screen tag value change touch detected display list swap occurred 4.2 system clock 4.2.1 clock source the ft81x can be co nfigured to use any of the three clock source s for system clock: ? internal relaxation oscillator clock (default) ? external 12mhz crystal ? external 12mhz square wave clock figure 4 - 4 , figure 4 - 5 and figure 4 - 6 show the pin connections for these clock options.
copyright ? 2015 future technology devices international limited 21 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 4 - 4 internal relaxation oscillator connection figure 4 - 5 crystal oscillator connection figure 4 - 6 external c lock i nput 4.2.2 phase locked loop the internal pll takes an input clock from the oscillator , and generates clock s to all internal circuits, incl uding the graphics engine, audio engine and touch engine . 4.2.3 clock enable at power - on the ft81x enters sleep mode. the internal relaxation oscillator is selected for the pll clock source. the system clock will be enabled when the following step is executed: ? host sends an active command if the application choose s to use the external clock source (12mhz crystal or clock), the following steps shall be executed: ? host sends a clkext command ? host sends an active command
copyright ? 2015 future technology devices international limited 22 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.2.4 clock frequency by default the system clock is 60 mhz when the input clock is 12mhz . the h ost is allowed to switch the system clock to other frequencies (48mhz, 36mhz, 24mhz) by the host command clksel . the clock switching command shall be sent in sleep mode only. when using the internal relaxation oscillator, its clock frequency is trimmed to be 12mhz at factory. software is allowed to chan ge the frequency to a lower value by programming the register reg_trim. note that software shall not change the internal oscillator frequency to be higher than 12mhz. 4.3 graphics engine 4.3.1 introduction the g raphics engine executes the display list once for ever y horizontal line. it executes the primitive objects in the display list and constructs the display line buffer. the horizontal pixel content in the line buffer is updated if the object is visible at the horizontal line. main features of the graphics engi ne are: ? the primitive objects supported by the graphics processor are: l ines, points, rectangles, bitmaps (comprehensive set of formats), text display, plotting bar graph, edge strips, and line strips, etc. ? operations such as stencil test, alpha blending a nd masking are useful for creating a rich set of effects such as shadows, transitions, reveals, fades and wipes. ? anti - aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer. ? bitmap transformations enable operations such a s translate, scale and rotate. ? display pixels are plotted with 1/16 th pixel precision. ? four levels of graphics states ? tag buffer detection the graphics engine also supports customized buil t - in widgets and functionalities such as jpeg decode, screen save r, calibration etc. the graphics engine interprets commands from the mpu host via a 4 kbyte fifo in the ft81x memory at ram_cmd . the mpu/mcu writes commands into the fifo, and the graphics engine reads and executes the commands. the mpu/mcu updates th e register reg_cmd_write to indicate that there are new commands in the fifo, and the graphics engine updates reg_cmd_read after commands have been executed. main features supported are: ? drawing of widgets such as buttons, clock, keys, gauge s , text displa y s, progress bars, sliders, toggle switches, dials, gradients, etc. ? jpeg and motion - jpeg decode ? inflate functionality (zlib inflate is supported) ? timed interrupt (generate an interrupt to the host processor after a specified number of milliseconds) ? in - bu ilt animated functionalities such as displaying logo, calibration, spinner, screen saver and sketch ? snapshot feature to capture the current graphics display for a complete list of graphics engine display commands and widgets refer to ft 81x_series_programmer_guide , chapter 4. 4.3.2 rom and ram fonts the ft81x has built in rom character bitmaps as font metrics. the graphic s engine can use these metrics when drawing text fonts. there are a total of 1 9 rom fonts, numbered with font handle 16 - 3 4 . the user can define and load customized font metrics into ram_g, which can be used by display command with handle 0 - 1 5 . each font metric block has a 148 byte font table which defines the parameters of the font and the pointer of font image . the font table format is shown in table 4 - 7 .
copyright ? 2015 future technology devices international limited 23 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 table 4 - 7 font table format address offset size(byte) parameter description 0 128 width of each font character, in pixels 128 4 font bitmap format, for example l1 , l4 or l8 132 4 font line strid e, in bytes 136 4 font width, in pixels 140 4 font height, in pixels 144 4 pointer to font image data in memory the rom font s are stored in the memory space rom_font. the rom font table is also stored in the rom. the starting address of the rom font t able for font index 16 is stored at rom_font_addr , with other font tables follow ing . the rom font table and individual character width (in pixel) are listed in table 4 - 8 through table 4 - 10 . f ont index 16, 18 and 20 - 31 are for basic ascii characters ( code 0 - 127), while font index 17 and 19 are for extended ascii characters ( code 128 - 255). the character wi dth for font index 1 6 through 19 is fixed at 8 pixels for any of the ascii characters. table 4 - 8 rom font table font index 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 font format l 1 l 1 l 1 l 1 l 1 l 1 l 1 l 1 l 1 l 1 l 4 l 4 l 4 l 4 l 4 l 4 l 4 l 4 l 4 line stride 1 1 1 1 2 2 2 3 3 4 7 8 9 1 1 1 4 1 8 2 3 3 0 3 9 font width (max) 8 8 8 8 1 1 1 3 1 7 1 8 2 5 3 4 1 3 1 5 1 9 2 1 2 8 3 7 4 9 6 3 8 2 font height 8 8 1 6 1 6 1 3 1 7 2 0 2 2 2 9 3 8 1 6 2 0 2 5 2 8 3 6 4 9 6 3 8 3 1 0 8 image pointer start address (hex) 2ff7fc 2ffbfc 2fe7fc 2fe f fc 2fdafc 2fcd3c 2fbd7c 2fa17c 2f7e3c 2f3d1c 2f181c 2ed61c 2e799c 2dfbbc 2d263c 2bac3c 2945fc 251e1c 1e1b5c table 4 - 9 rom font ascii character width in pixels font index => 16/ 18 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 ascii character width in pixels 0 null 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 soh 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 stx 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 etx 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 eot 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 enq 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 ack 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 bel 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 bs 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ht 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 lf 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 vt 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 ff 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 cr 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 so 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 si 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 dle 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 dc1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 dc2 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 dc3 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 dc4 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
copyright ? 2015 future technology devices international limited 24 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 font index => 16/ 18 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 21 nak 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 22 syn 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 etb 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 can 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 em 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 26 sub 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 esc 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 fs 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 gs 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 rs 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 us 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 spac e 8 3 4 5 5 6 9 3 4 5 6 8 10 13 18 23 33 ! 8 3 4 5 6 6 9 3 4 6 6 9 11 15 19 25 34 " 8 4 5 6 5 8 12 5 6 7 8 12 15 19 25 33 35 # 8 6 8 9 10 14 19 10 11 14 15 19 26 33 44 57 36 $ 8 6 8 9 10 13 18 8 10 11 15 18 25 31 41 54 37 % 8 9 12 14 16 22 29 11 13 16 17 23 31 40 52 68 38 & 8 8 10 11 13 17 22 9 11 14 15 19 26 34 44 57 39 ' 8 2 3 3 3 6 6 3 4 4 5 7 10 11 15 20 40 ( 8 4 5 6 6 8 11 5 6 7 9 11 15 18 24 31 41 ) 8 4 5 6 6 8 11 5 6 8 8 10 14 18 24 31 42 * 8 4 7 6 7 10 13 7 8 10 11 14 18 24 31 4 0 43 + 8 6 9 10 10 14 19 9 10 12 14 17 24 30 41 52 44 , 8 3 3 4 5 6 9 3 4 4 5 7 9 12 16 20 45 - 8 4 4 5 6 8 11 6 7 10 11 15 18 24 32 41 46 . 8 3 3 4 5 6 9 3 4 6 7 8 11 14 19 24 47 / 8 3 4 5 5 7 9 6 7 9 10 13 17 22 29 38 48 0 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 49 1 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 50 2 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 51 3 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 52 4 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 53 5 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 54 6 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 55 7 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 56 8 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 57 9 8 6 8 9 10 13 18 8 10 12 14 17 24 30 40 52 58 : 8 3 3 4 5 6 9 3 4 6 6 7 10 13 18 23 59 ; 8 3 4 4 5 6 9 3 4 6 6 8 10 14 18 23 60 < 8 6 8 10 10 15 19 8 9 11 12 16 21 28 36 46 61 = 8 5 9 10 11 15 19 8 9 13 14 18 23 30 40 52 62 > 8 6 8 10 10 15 19 8 9 11 13 16 2 2 29 37 48 63 ? 8 6 8 9 10 12 18 7 9 10 12 15 20 26 34 44 64 @ 8 11 13 17 18 25 34 13 15 19 21 28 37 49 63 82 65 a 8 7 9 11 13 17 22 9 11 13 15 20 27 34 45 58 66 b 8 7 9 11 13 17 2 2 9 10 14 15 19 27 34 45 58 67 c 8 8 10 12 14 18 24 9 11 13 15 20 26 34 45 58 68 d 8 8 10 12 14 18 24 9 11 14 17 22 28 36 48 63 69 e 8 7 9 11 13 16 22 7 9 12 13 16 23 29 39 50 70 f 8 6 8 10 12 14 20 7 9 12 13 17 22 29 39 50 71 g 8 8 11 13 15 19 25 9 11 14 16 22 28 37 48 62 72 h 8 8 10 12 14 18 24 9 11 15 17 23 29 37 50 65 73 i 8 3 4 4 6 8 9 4 5 6 7 9 12 15 2 0 26 74 j 8 5 7 8 10 13 16 8 9 12 13 17 23 30 40 50 75 k 8 7 9 11 13 18 22 9 11 14 16 19 26 34 45 58
copyright ? 2015 future technology devices international limited 25 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 font index => 16/ 18 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 76 l 8 6 8 9 11 14 18 7 9 12 13 17 22 29 39 51 77 m 8 9 12 13 16 21 27 11 14 1 9 21 26 35 46 62 79 78 n 8 8 10 12 14 18 24 9 11 15 17 23 29 37 50 65 79 o 8 8 11 13 15 18 25 10 12 14 16 22 28 37 49 63 80 p 8 7 9 11 13 16 22 9 10 14 15 19 26 34 45 58 81 q 8 8 1 1 13 15 18 26 10 12 14 17 22 29 38 50 64 82 r 8 7 10 12 14 17 24 9 11 13 15 19 27 33 45 58 83 s 8 7 9 11 13 16 22 9 11 12 14 20 26 33 43 56 84 t 8 5 9 10 12 16 20 10 12 14 15 19 26 32 42 56 85 u 8 8 10 12 14 18 24 9 11 13 17 21 28 37 48 62 86 v 8 7 9 11 13 17 22 9 11 14 15 20 27 34 45 58 87 w 8 9 13 15 18 22 31 12 15 18 21 27 36 46 61 79 88 x 8 7 9 11 13 17 22 9 11 13 15 20 27 34 45 58 89 y 8 7 9 11 13 16 22 9 10 14 15 19 26 34 45 58 90 z 8 7 9 10 12 15 20 9 11 13 14 18 25 32 42 55 91 [ 8 3 4 5 5 7 9 4 5 6 7 9 12 15 19 25 92 \ 8 3 4 5 5 7 9 6 7 9 10 13 18 22 29 38 93 ] 8 3 4 5 5 7 9 4 5 7 7 9 12 15 19 25 94 ^ 8 6 7 8 9 12 16 6 7 9 10 13 18 23 30 38 95 _ 8 6 8 9 11 14 18 8 10 11 13 16 21 26 34 43 96 ` 8 3 5 6 4 7 11 4 5 7 8 10 13 17 22 29 97 a 8 5 8 9 11 13 18 8 9 11 13 17 23 30 39 50 98 b 8 6 7 9 11 14 18 8 9 11 14 17 24 31 40 52 99 c 8 5 7 8 10 12 16 8 9 11 12 16 22 28 37 48 100 d 8 6 8 9 11 14 18 8 10 12 14 17 24 31 40 52 101 e 8 5 8 9 10 13 18 8 9 11 12 16 22 29 37 48 102 f 8 4 4 5 6 8 9 6 7 8 10 12 15 19 25 31 103 g 8 6 8 9 11 14 18 8 10 11 14 18 24 31 41 52 104 h 8 6 8 9 10 13 18 8 9 11 14 17 24 31 41 52 105 i 8 2 3 3 4 6 7 3 4 6 6 7 10 13 18 23 106 j 8 2 3 4 4 6 7 3 4 6 6 8 11 14 18 23 107 k 8 5 7 8 9 12 16 7 9 11 13 16 22 28 36 47 108 l 8 2 3 3 4 6 7 3 4 6 6 7 10 13 18 23 109 m 8 8 11 14 16 20 27 11 15 18 21 27 36 47 63 80 110 n 8 6 8 9 10 14 18 8 9 11 14 17 24 31 41 52 111 o 8 6 8 9 11 13 18 8 10 12 13 17 24 31 40 52 112 p 8 6 8 9 11 14 18 8 9 11 14 17 24 31 40 51 113 q 8 6 8 9 11 14 18 8 10 12 13 17 24 31 40 52 114 r 8 4 5 5 6 9 11 5 6 7 9 11 15 19 25 32 115 s 8 5 7 8 9 12 16 7 9 11 12 17 22 29 38 48 116 t 8 4 4 5 6 8 9 6 7 8 9 11 14 17 23 29 117 u 8 5 7 9 10 14 18 8 9 12 14 17 24 31 41 52 118 v 8 6 7 8 10 13 16 7 9 11 12 16 21 27 36 46 119 w 8 8 10 12 14 18 23 11 13 16 18 23 32 41 54 70 120 x 8 6 7 8 10 12 16 7 9 11 12 16 21 27 36 46 121 y 8 5 7 8 10 13 16 7 9 11 12 16 21 27 36 46 122 z 8 5 7 8 9 12 16 8 9 11 12 15 22 27 36 46 123 { 8 3 5 6 6 8 11 5 6 8 8 11 15 18 24 31 124 | 8 3 3 4 5 6 9 3 4 5 6 7 10 14 18 23 125 } 8 3 5 6 6 8 11 5 6 7 9 10 15 18 24 31 126 ~ 8 7 8 10 10 14 19 10 11 14 15 21 29 36 47 63 127 del 8 0 0 0 0 0 0 3 4 5 6 5 10 13 18 23 table 4 - 10 rom font extended ascii characters
copyright ? 2015 future technology devices international limited 26 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 decimal symbol decimal symbol decimal symbol decimal symbol decimal symbol decimal symbol decimal symbol decimal symbol 128 ? 144 160 176 ? 192 208 e 224 240 - 129 145 ? 161 177 ? 193 209 e 225 ? 241 130 146 ? 162 178 194 210 226 ? 242 ? 131 a 147 ? 163 179 195 211 ? 227 243 ? 132 ? 148 ? 164 ? 180 196 212 228 ? 244 ? 133 149 1 65 ? 181 197 213 ? 229 ? 245 134 ? 150 ? 166 a 182 a 198 ? 214 230 246 135 ? 151 167 o 183 199 ? 215 ? 231 t 247 ? 136 152 ? 168 ? 184 ? 200 ^ 216 ? 232 t 248 137 ? 153 ? 169 ? 185 g 201 X 217 233 249 138 154 170 ? 186 U 202 m 218 234 ? 250 139 ? 155 ? 171 ? 187 [ 203 j 219 235 251 1 140 ? 156 172 ? 188 a 204 d 220 { 236 y 252 3 141 157 ? 173 ? 189 205 T 221 | 237 y 253 2 142 ? 158 174 ? 190 206 p 222 238 254 143 ? 159 ? 175 ? 191 207 223 ? 239 255 nbsp note: font 17 and 19 are extended ascii characters, with width fixed at 8 pixels for all characters. note: all fonts included in the ft81x rom are widely available to the market - place for general usage . s ee section nine for specifi c copyright data and links to the corresponding license agreements. 4.4 parallel rgb interface the rgb parallel interface consist s of 23 or 29 signal s - disp , pclk, vsync, hsync, de, 6 or 8 signals each for r, g and b. a set of rgb registers configu re the lcd operation and timing parameter s. reg_ pclk is the pclk divisor . t he default value is 0, which means the pclk output is disabled . when reg_pclk is none 0 (1 - 1023), the pclk frequency can be calculated as : pclk frequen cy = system clock frequency / reg_pclk the ft81x system clock frequency is programmable . some of t he possible pclk frequencies that ft81x supports are listed in table 4 - 11 . table 4 - 11 rgb pclk frequency reg_pclk system clock frequency (mhz) 60 (default) 48 36 24 1 60 48 36 24 2 30 24 18 12 3 20 16 12 8 .0 4 15 12 9 .0 6 .0 5 12 9.6 7.2 4.8 6 10 8 .0 6 .0 4 .0 7 8.6 6.9 5.1 3.4
copyright ? 2015 future technology devices international limited 27 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 reg_pclk system clock frequency (mhz) 60 (default) 48 36 24 8 7.5 6 .0 4.5 3 .0 9 6.7 5.3 4.0 2.7 10 6.0 4.8 3.6 2.4 reg_ pclk_pol define s the clock polarity , with 0 for positive active clock edge, and 1 for negative clock edge. reg_cspread control s the transition of rgb signals with respect to the pclk active clock edge . w hen reg_cspread=0, r[7: 0 ] , g[7: 0 ] and b[7: 0 ] signal s change following the active edge of pclk. when reg_cspread=1, r[7: 0 ] change s a pclk clock early and b[7: 0 ] a pclk clock later , which help s reduce the switching noise . reg_dither enables colo u r dither . t his option improves the half - tone appearance on displays. internally, the graphics engine compute s the colo u r values at an 8 bit precision; however, the lcd colour at a lower precision is sufficient . the ft81 0/ft811 output is only 6 bits per colo u r in 6:6: 6 formats and a 2x2 dither matrix allow the truncated bits to contribute to the final colo u r value s . reg_outbits gives the bit width of each colour channel, the default is 6 / 6 / 6 (for ft810/ft811) or 8 / 8 / 8(for ft812/ft813) bits for each r / g / b colo u r. a lower value means fewer bits are output for each channel allowing dither ing o n lower precision lcd displays . reg_swizzle controls the arrangement of the output colo u r pins, to help the pcb route different lcd panel arrangements. bit 0 of the register cau ses the order of bits in each colo u r channel to be reversed. bits 1 - 3 control the rgb order. setting bit 1 causes r and b channels to be swapped . setting bit 3 allows rotation to be enabled . if b it 3 is set, then (r,g,b) is rotated right if bit 2 is one, o r left if bit 2 is zero. table 4 - 12 reg_swizzle rgb pins mapping reg_swizzle pins (ft810/ft811, 6 bits) pins (ft812/ft813, 8 bits) b3 b2 b1 b0 r7 , r6 , r5 , r 4 , r3 , r2 g7 , g6 , g5 , g4 , g3 , g2 b7 , b6 , b5 , b4 , b3 , b2 r7 , r6 , r5 , r4 , r3 , r2 , r1, r0 g7 , g6 , g5 , g4 , g3 , g2 , g1, g0 b7 , b6 , b5 , b4 , b3 , b2 , b1, b0 0 x 0 0 r[7:2] g[7:2] b[7:2] r[7: 0 ] g[7: 0 ] b[7: 0 ] 0 x 0 1 r[2:7] g[2:7] b[2:7] r[ 0 :7] g[ 0 :7] b[ 0 :7] 0 x 1 0 b[7:2] g[7:2] r [7:2] b[7: 0 ] g[7: 0 ] r [7: 0 ] 0 x 1 1 b[ 2 : 7 ] g[ 2 : 7 ] r [ 2 : 7 ] b[ 0 : 7 ] g[ 0 : 7 ] r [ 0 : 7 ] 1 0 0 0 b[7:2] r[7:2] g[7:2] b[7: 0 ] r[7: 0 ] g[7: 0 ] 1 0 0 1 b[ 2 : 7 ] r[ 2 : 7 ] g[ 2 : 7 ] b[ 0 : 7 ] r[ 0 : 7 ] g[ 0 : 7 ] 1 0 1 0 g[7:2] r[7:2] b[7:2] g[7: 0 ] r[7: 0 ] b[7: 0 ] 1 0 1 1 g[ 2 : 7 ] r[ 2 : 7 ] b[ 2 : 7 ] g[ 0 : 7 ] r[ 0 : 7 ] b[ 0 : 7 ] 1 1 0 0 g[7:2] b[7:2] r[7:2] g[7: 0 ] b[7: 0 ] r[7: 0 ] 1 1 0 1 g[ 2 : 7 ] b[ 2 : 7 ] r[ 2 : 7 ] g[ 0 : 7 ] b[ 0 : 7 ] r[ 0 : 7 ] 1 1 1 0 r[7:2] b[7:2] g[7:2] r[7: 0 ] b[7: 0 ] g[7: 0 ] 1 1 1 1 r[ 2 : 7 ] b[ 2 : 7 ] g[ 2 : 7 ] r[ 0 : 7 ] b[ 0 : 7 ] g[ 0 : 7 ] reg_h cycle, reg_hsize, reg_hoffset, reg_hsync0 and reg_hsync1 define the lcd horizontal timings. each register has 12 bits to allow programmable range of 0 - 4095 pclk cycles. reg_vcycle, reg_vsize, reg_voffset, reg_vsync0 and reg_ v sync1 define the lcd vertical t imings. each register has 12 bits to allow programmable range of 0 - 4095 lines . table 4 - 13 registers for rgb horizontal and vertical timings
copyright ? 2015 future technology devices international limited 28 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 register display parameter description horizontal reg_hcycle t h total length of line (visible and non - visible) (in pclks) reg_hsize t hd length of visible part of line (in pclks) reg_hoffset t hf + t hp + t hb length of non - visible part of line (in pclk cycles) reg_hsync0 t hf horizontal front porch (in pclk cycles) reg_hsync1 t hf + t hp horizontal front porch plus hsync pulse width (in pclk cycles) vertical reg_vcycle t v total number of lines (visible and non - visible) (in lines) reg_vsize t vd number of visible lines (in lines) reg_voffset t vf + t vp + t vb number of non - visible lines (in lines) reg_vsync0 t vf vertical front porch (in lines) reg_vsync1 t vf + t vp vertical front porch plus vsync pulse width (in lines) figure 4 - 7 rgb timing waveforms 4.5 miscellan eous control
copyright ? 2015 future technology devices international limited 29 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.5.1 backlight control pin the backlight dimming control pin (backlight) is a pulse width modulated (pwm) signal controlled by two registers: reg_pwm_hz and reg_pwm_duty . r eg_pwm_hz specifies the pwm output frequency, the range is 250 - 10000 hz. re g_pwm_duty specifies the duty cycle; the range is 0 - 128. a value of 0 means that the pwm is completely off and 128 means completely on. the backlight pin will output low when the disp pin is not enabled ( i.e. logic 0). 4.5.2 disp control pin the disp pin is a general purpose output that can be use d to enable , or reset the lcd display panel. the pin is control led by writing to bit 7 of the reg_gpio register , or bit 15 of reg_gpiox . 4.5.3 general purpose io pins depending on the package, the ft8 1x can be configured to use up to 4 gpio pins. these gpio pins are controlled by the reg_gpiox_dir and reg_gpiox registers . alternatively the gpio0 and gpio1 pins can also be controlled by reg_gpio_dir and reg_gpio to maintain backward compatib ility with t he ft800/ft801. when the qspi is enabled in quad mode, gpio0/io2 and gpio1/io3 pins are used as data lines of the qspi. 4.5.4 pins drive current control the output drive current of output pins can be change d as per the follow ing table by writing to b it[6: 2] of reg_gpio register or bit[14:10] of reg_gpiox register . alternatively, use the spi command pin drive to change the individual pin drive strength. table 4 - 14 output drive current selection reg_gpio bit[6:5] bit[4] bit[3:2] reg_gpio x bit[ 14 : 13 ] bit[ 12 ] bit[ 11 : 10 ] value 00b # 01b 10b 11b 0b # 1b 00b # 01b 10b 11b drive current 5 m a 10 ma 15 ma 20 ma 5 ma 10 ma 5 ma 10 ma 1 5 ma 20 ma pins gpio 0 gpio 1 gpio2 gpio3 ctp_rst_n pclk disp vsync hsync de r7.. r0 g7.. g0 b7.. b0 backlight miso mosi io2 io3 int_n note : # default value
copyright ? 2015 future technology devices international limited 30 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.6 audio engine ft81x provide s mono audio output through a pwm output pin, audio_l. it output s two audio sources, the sound synth esi zer and audio file playback. 4.6.1 sound synthesizer a sound processor, audio engine , generate s the sound effects from a s mall rom library of wave s table . to play a sound effect listed in table 4.3 , load the reg _ sound register with a code value and write 1 to the reg _ play register. the reg _ play register reads 1 while the effect is playing and return s a 0 when the effect end s . some sound effect s play continuously u ntil interrupted or instruct ed to play the next sound effect. to interrupt an ef fect, write a new value to reg _ sound and reg _ play registers ; e . g . write 0 (silence) to reg_sound and 1 to peg_play to stop the sound effect. the sound volume is controlled by register reg_vol_sound. the 16 - bit reg _ sound register takes an 8 - bit sound in the low byte. for some sounds, marked "pitch adjust" in the table below, the high 8 bits contain a midi note value. for these sounds, a note value of zero indicates middle c. for other sounds the high byte of reg _ sound is ignored. table 4 - 15 sound effect value effect conti nuous pitch adjust value effect conti nuous pitch adjust 00h silence y n 32h dtmf 2 y n 01h square wave y y 33h dtmf 3 y n 02h sine wave y y 34h dtmf 4 y n 03h sawtooth wave y y 35h dtmf 5 y n 04h triangle wave y y 36h dtmf 6 y n 05h beeping y y 37h dtmf 7 y n 06h alarm y y 38h dtmf 8 y n 07h warble y y 39h dtmf 9 y n 08h carousel y y 40h harp n y 10h 1 short pip n y 41h xylo phone n y 11h 2 short pips n y 42h tuba n y 12h 3 short pips n y 43h glockenspiel n y 13h 4 short pips n y 44h organ n y 14h 5 short pips n y 45h trumpet n y 15h 6 short pips n y 46h piano n y 16h 7 short pips n y 47h chimes n y 17h 8 short pi ps n y 48h music box n y 18h 9 short pips n y 49h bell n y 19h 10 short pips n y 50h click n n 1ah 11 short pips n y 51h switch n n 1bh 12 short pips n y 52h cowbell n n 1ch 13 short pips n y 53h notch n n 1dh 14 short pips n y 54h hihat n n 1eh 15 short pips n y 55h kickdrum n n 1fh 16 short pips n y 56h pop n n 23h dtmf # y n 57h clack n n 2ch dtmf * y n 58h chack n n 30h dtmf 0 y n 60h mute n n 31h dtmf 1 y n 61h unmute n n
copyright ? 2015 future technology devices international limited 31 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 table 4 - 16 midi note effect midi note ansi note f req (hz) midi note ansi note f req (hz) 21 a0 27.5 65 f4 349.2 22 a#0 29.1 66 f#4 370.0 23 b0 30.9 67 g4 392.0 24 c1 32.7 68 g#4 415.3 25 c#1 34.6 69 a4 440.0 26 d1 36.7 70 a#4 466.2 27 d#1 38.9 71 b4 493.9 28 e1 41.2 72 c5 523.3 29 f1 43.7 73 c#5 554.4 30 f#1 46.2 74 d5 587.3 31 g1 49.0 75 d#5 622.3 32 g#1 51.9 76 e5 659.3 33 a1 55.0 77 f5 698.5 34 a#1 58.3 78 f#5 740.0 35 b1 61.7 7 9 g5 784.0 36 c2 65.4 80 g#5 830.6 37 c#2 69.3 81 a5 880.0 38 d2 73.4 82 a#5 932.3 39 d#2 77.8 83 b5 987.8 40 e2 82.4 84 c6 1046.5 41 f2 87.3 85 c#6 1108.7 42 f#2 92.5 86 d6 1174.7 43 g2 98.0 87 d#6 1244.5 44 g#2 103.8 88 e6 1318.5 45 a2 110.0 89 f6 1396.9 46 a#2 116.5 90 f#6 1480.0 47 b2 123.5 91 g6 1568.0 48 c3 130.8 92 g#6 1661.2 49 c#3 138.6 93 a6 1760.0 50 d3 146.8 94 a#6 1864.7 51 d#3 155.6 95 b6 1975.5 52 e3 164.8 96 c7 2093.0 53 f3 174.6 97 c#7 2217.5 54 f#3 185. 0 98 d7 2349.3 55 g3 196.0 99 d#7 2489.0 56 g#3 207.7 100 e7 2637.0 57 a3 220.0 101 f7 2793.8 58 a#3 233.1 102 f#7 2960.0 59 b3 246.9 103 g7 3136.0 60 c4 261.6 104 g#7 3322.4 61 c#4 277.2 105 a7 3520.0 62 d4 293.7 106 a#7 3729.3 63 d#4 31 1.1 107 b7 3951.1 64 e4 329.6 108 c8 4186.0
copyright ? 2015 future technology devices international limited 32 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.6.2 audio p layback the ft81x can play back recorded sound through its audio output. to do this, load the original sound data into the ft81x s ram , and set registers to start the playback. the regist ers controlling audio playback are: reg _ playback _ start: the start address of the audio data reg _ playback _ length: the length of the audio data, in bytes reg _ playback _ freq: the playback sampling frequency, in hz reg _ playback _ format: the playback form at, one of linear samples, ulaw samples, or adpcm samples reg _ playback _ loop: if zero, the sample is played once. if one, the sample is repeated indefinitely reg _ playback _ play: a write to this location triggers the start of audio playback , r egardless of writing 0 or 1 . read back 1 when playback is ongoing, and 0 when playback finishes reg _ vol _ pb: playback volume, 0 - 255 the mono audio format s supported are 8 - bits pcm, 8 - bits ulaw and 4 - bits im a - adpcm. for adpcm _ samples , each sample is 4 bits, so two samples are packed per byte , the first sample is in bit s 0 - 3 and the second is in bit s 4 - 7. the current audio playback read pointer can be queried by reading the reg _ playback _ readptr. using a large sample buffer, looping, and this read pointer, the host mpu /mcu can supply a continuous stream of audio. 4.7 touch - s creen engine the ft81x touch - screen engine supports both resistive and capacitive touch panels. ft810 and ft812 support resistive touch, while ft811 and ft813 support capacitive touch. 4.7.1 resistive touch control the resistive touch - screen consists of a touch screen engine, adc, axis - switches, and adc input multiplexer. the touch screen engine reads commands from the memory map registe r and generates the required control signals to the axis - switches and inputs mux and adc. the adc data are acquired , processed and update d in the respective register for the mpu/mcu to read. figure 4 - 8 resistive touch screen connection y+ y - x - x+ ft810/ ft812 xp yp xm ym resistive touch screen
copyright ? 2015 future technology devices international limited 33 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 the host controls the touch screen engine operation mode by writing the reg_touch_mode. table 4 - 17 resistive touch controller operating mode reg_touch_mode mode description 0 off acquisition stopped, only touch detection interrupt is still valid. 1 one - shot perform acquisition once every time the mpu write s '1' to reg_t ouch_mode. 2 frame - sync perform acquisition for every frame sync (~60 data acquisition/second. 3 continuous perform acquisition continuously at approximately 1000 data acquisition / second. the touch screen engine captures the raw x and y coordinate an d writes to register reg_touch_raw xy. the range of these values is 0 - 1023. if the touch screen is not being pressed, both registers read 65535 (ffffh). these touch values are transformed into screen coordinates using the matrix in registers reg_touch_tran sform_a - f. the post - transform coordinates are available in register reg_touch_screen_xy. if the touch screen is not being pressed, both registers read - 32768 (8000h). the values for reg touch transform a - f may be computed using an on - screen calibration pro cess. if the screen is being touched, the screen coordinates are looked up in the screen's tag buffer, delivering a final 8 - bit tag value, in reg touch tag. because the tag lookup takes a full frame, and touch coordinates change continuously, the original (x; y) used for the tag lookup is also available in reg_touch_tag_xy. screen touch pressure is available in reg_touch_rz. the value is relative to the resistance of the touch contact, a lower value indicates more pressure. the register defaults to 32767 wh en touch is not detected. the reg_touch_threshold can be set to accept a touch only when the force threshold is exceeded. 4.7.2 capacitive touch control the capacitive touch screen e ngine (ctse) of the ft81x communicates with the external capacitive touch panel module (ctpm) through an i 2 c interface. the ctpm will assert its interrupt line when there is a touch detected. upon detecting ctp_int_n line active, the ft81x will read the touch data through i 2 c. up to 5 touches can be reported and stored in ft81x registers. for a suppo r ted ctpm list please consult ftdi website .
copyright ? 2015 future technology devices international limited 34 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 4 - 9 tou ch screen connection the host control s the ctse operation mode by writing the reg_ c touch_mode. table 4 - 18 capacitive touch controller operating mode reg_ c touch_mode mode description 0 off a cquisition stop ped 1 - 2 reserved reserved 3 continuous perform acquisition continuously at the reporting rate of the connected ctpm . the ft81x ctse supports compatibility mode and extended m ode. by default the ctse runs in compatibility mode where the touch system provides an interface very similar to the resistive touch engine . in this mode the same a pplication code can run on ft810/ft812 and ft81 1/ft813 without alteration. in extended mode, the touch register meanings are modified, and a second set of registers are exposed. these allow multi - touch detection (up to 5 touches) . 4.7.3 compatibility mode the ctse reads the x and y coordinate s from the ctpm and write s to register reg_ c touch_ raw_ xy. if the touch screen is not being pressed, both registers read 65535 (ffffh) . these touch values are transformed into screen coordinates using the matrix in registers reg _ c touch_transform_a - f. the post - transform coordinate s are available in register reg_ c to uch_screen_ xy. if the touch screen is not being pressed, both registers read - 32768 ( 8000h ) . the values for reg_c touch _ transform _ a - f may be computed using an on - screen calibration process. if the screen is being touched, the screen coordinates are looked u p in the screen's tag buffer, delivering a final 8 - bit tag value, in reg_touch_ tag. because the tag lookup takes a full frame, and touch coordinates change continuously, the original (x; y) used for the tag lookup is also available in reg _ touch _ tag _ xy. 4.7.4 ex tended mode setting reg_ctouch_extended to 1b 0 enable s extended mode. in extended mode a new set of readout registers are available, allowing gesture s and up to five touches to be read. there are two classes of registers: control registers and status regi sters. control registers are written by the mcu. status registers can be read out by the mcu and the ft81x s hardware tag system. scl rstn sda intn ft811/ ft813 ctp_scl ctp_sda ctp_int_n ctp_rst_n capacitive touch panel module vccio2 (1.8 - 3.3v) 1 k 1 k
copyright ? 2015 future technology devices international limited 35 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 the five touch coordinates are packed in reg_ctouch_touch 0 _xy, reg_ctouch_touch 1 _xy, reg_ctouch_touch 2 _xy , reg_ctouch_tou ch 3 _xy , reg_ctouch4_x and reg_ctouch4_y. coordinates stored in these registers are signed 1 6 - bit values, so have range - 32768 to 32767 . the no - t ouch condition is indicated by x=y= - 32768 . these coordinates are already transformed into screen coordinates b ased on the raw data read from the ctpm, using the matrix in registers reg_ctouch_transform_a - f. to obtain raw (x,y) coordinates read from ctpm , the user sets the reg_ctouch_transform_a - f registers to the identity matrix. the ft81x tag mechanism is im plemented by hardware, w here up to 5 tags can be looked up . 4.7.5 short - circuit protection for resistive touch it is useful to protect the chip from permanent damage due to potential short - circuits on the 4 xy lines . when a shor t circuit on the touch screen happens , the ft81x can detect it and stop the touch detection op eration, leaving the 4 xy pins in the high impedance state. the short - circuit protection can be enabled/disabled by the reg_touch_config. 4.7.6 c apacitive touch configur ation on capacitive touch system some users may need to adjust the ctp m default values , suc h as the registers affecting touch sensitivity. to do this t he following sequence shall be executed once after chip reset : - hold the touch engine in reset (set reg_cpureset = 2) - write the ctp m configure register address and value to ft81x designated memory location - up to 10 register address/value can be added - release the touch engine reset (set reg_cpureset = 0) the ctp m can be enabled in low power state when the touch function is not required by the application. s et ting the low - power bit in reg _ touc h _ c onfig will enable the low power mode of the ctpm. when the low - power bit is cleared, the ft81x touch engine will send a reset to the ctpm, thus re - enabl ing the touch detection function. 4.7.7 touch detection in none - active state when ft81x is in none - active st ate, a touch event can still be detected and reported to the host through the int_n pin. in other words, a touch event can wake - up the host if needed. for resistive touch, the int_n pin will be asserted low when the screen is touched , regardless of the set ting of the interrupt register s . this will happen when the ft81x is in standby or sleep state, but not in powerdown state. for capacitive touch, the int_n pin will follow ctp_int_n pin when the ft81x is in standby, sleep or powerdown state. 4.8 power managem ent 4.8.1 power supply the ft81x may be operated with a single supply of 3.3v appl ied to vcc and vccio pins. for operation with a host mpu /mcu at a lower supply, connect the vccio 1 to the mpu io supply to match the interface voltage . for operation with lcd/ touch panel s at lower voltage s , connect the vccio2 to the lcd/touch io supply.
copyright ? 2015 future technology devices international limited 36 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 table 4 - 19 power supply symbol typical description vccio1 1.8v, or 2.5v, or 3 .3v supply for host interface digital i/o pins vcc io 2 1.8v, or 2.5v, or 3.3v supply for rgb and touch interface i/o pins vcc 3.3v supply for 3.3v circuits and internal regulator vout1v2 1.2 v supply for digital core. generated by internal regul ator 4.8.2 internal regulator and por the internal regulator provide s power to the core circuit. a 47k ? resistor is recommended to pull the pd_n pin up to vccio 1 , together with a 100nf capacitor to ground in order to delay the internal regulat or powering up after the vcc and vccio are stable. the internal regulator requires a compensation capacitor to be stable. a typical design requires a 4.7 uf capacitor between the vout1v2 and gnd pins. do no t connect any other load t o the vout1v2 pin. the internal regulator will generate a power - on - reset (por) pulse when the output voltage rises above the por threshold. the por will reset all the core digital circuits. it is possible to use pd_n pin as an asynchronous hardwar e reset input. drive pd_n low for at least 5ms and then drive it high will reset the ft81x chip. figure 4 - 10 internal regulator vcc pd_n g n d vout1v2 vcc gnd gnd gnd vccio1 c 1 r 1 c 2 10uf 100nf g nd c 3 4.7uf 47k ft81x
copyright ? 2015 future technology devices international limited 37 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.8.3 power mode s when the supply to vccio and vcc is applied, the internal regulator is powered by vcc. an internal por pulse will be generated during the regulator power up until it is stable. after the initial power up , the ft81x will stay in the slee p state . when needed, the host can set the ft81x to the active state by performing a spi active command . the graphics engine, the audio engine and the touch engine are only functional in the active state. to save power the host can send a command to put the ft81x into any of the low power mode s : standby, sleep and powerdown. in addition, the host is allowed to put the ft81x in powerdown mode by driv ing the pd_n pin to low, regardless of what state it is currently in. re fer to figure 4 - 11 f or the power state transitions. figure 4 - 11 power state transition 4.8.3.1 active state in active state , the ft81x is in normal operati on . the clock oscillator and pll are functioning. the system clock applied to the ft81x core engines is enabled. 4.8.3.2 standby state in standby state , th e clock oscillator and pll remain functioning; the system clock app lied to the ft81x core engines is disabled . all register content s are retained. 4.8.3.3 sleep state in sleep state , the clock oscillator , pll and system clock applied to the ft81x core engines are disabled . all register content s are retained. 4.8.3.4 powerdown state in powerdown state, the clock oscillator, the pll and the system clock applied to the ft81x core is disable d . the core engines are powered down while the sp i interface for host commands remains functional . all register content s are lost and reset to default when the chip is next switched on . the internal regulator remains on. powerdown sleep standby vcc/vccio power on toggle pd_n from high to low active toggle pd_n from low to high toggle pd_n from high to low toggle pd_n from high to low or write command powerdown write command standby write command sleep write command active write command active
copyright ? 2015 future technology devices international limited 38 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 4.8.3.5 w ake up to active from other power states when in the power down state, if the devi ce enters this state via an spi command, then only the spi active command will bring the device back to the active state, provided pd_n pin is also high. however, if pd_n is used instead, then making pd_n high followed by a spi active command will wake up the device. upon exiting this state, the device will perform a global reset, and will go through the same power up sequence. all settings from spi commands will be reset except those that pertain to pin state s during power down. the clock enable sequence mentioned in section 4.2.3 shall be executed to proper ly select and enable the system clock. from the sleep state, the host mpu sends an spi active command to wake the ft81x into th e active state. the h ost needs to wait for at least 20ms before accessing any registers or commands. this is to guarantee the clock oscillator and pll are up and stable. from the standby state, the host mpu sends spi active command to wake the ft81x into the active state. the h ost can immediately access any register or command. 4.8.4 reset and boot - up sequence there are a few hardware and software reset events which can be triggered to reset the ft81x . hardware reset events : ? power - on - reset( por ) ? toggle the pd_n pin software reset events: ? spi command rst_pulse ? spi command to switch between the internal clock and the external clock ? spi command to enter powerdown then wakeup after reset the ft81x will be in the sleep state. upon receiving an spi active command , the internal oscillator and pll will start up. once the clock is stable, the chip will check and repair its intern al ram, running the configur ation and release the clock to the system. the chip will exit the reset and boot - up state and enter into normal operations. the boot - up may take up to 300ms to complete. 4.8.5 pin s tatus at d ifferent p ower s tates the ft81x pin status depends on the power state of the chip. see the following table for more details. at the power transi tion from active to standby or active to sleep , all pins retain their previous status. the software needs to set audio_l , backlight to a known state before issuing power transition commands. the pin status in the power down state can be changed by spi comm and pin _pd_state. table 4 - 20 pin status pin name default drive reset normal power down (default) audio_l 20ma out, float out pull low sck - in in in miso 5ma out, float ( cs_n = 1) io out, float mosi 5ma in io in cs_n - in in in
copyright ? 2015 future technology devices international limited 39 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 pin name default drive reset normal power down (default) io2 gpio0 5ma 5ma in in io io float float io3 gpio1 5ma 5ma in in io io float float gpio2 5ma in io float int_n 5ma od, float od / out float pd_n - in in in gpio 3 5ma in io float x1/clk - in in in xp - io, float io float yp - io, float io float xm - io, float io float ym - io, float io float ctp_rst_n 5ma out out pull low ctp_int_n - in (internal pull - up) in (internal pull - up) in (i nternal pull - up) ctp_scl 20ma od io float ctp_sda 20ma od io float backlight 5ma out out pull low de 5ma out out pull low vsync 5ma out out pull low hsync 5ma out out pull low disp 5ma out out pull low pclk 5ma out out pull low r/g/b 5ma ou t out pull low
copyright ? 2015 future technology devices international limited 40 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 5 memory map all memory and registers in t he ft81x core are memory ma p p ed in 22 - bit address space with a 2 - bit spi command prefix . prefix 0'b00 for read and 0'b10 for write to the address space, 0'b 0 1 is reserved for host comm ands and 0'b11 undefined . the following are the memory space defin ition . table 5 - 1 ft81x memory map start address end address size name description 00 0000h 0 f ffffh 1024 k b ram_g general purpose graphics ram 1e 000 0h 2f fff b h 1 152 kb rom_font font table and bitmap 2f fffc h 2 f fff f h 4 b rom_font_ addr font table pointer address 3 0 0 000h 3 0 1ff fh 8 kb ram_ d l display list ram 3 0 20 00 h 3 0 2ff fh 4 k b ram_reg registers 3 0 8 000 h 3 0 8fff h 4 kb ram_cmd command buffer n ote 1 : the addresses beyond this table are reserved and shall not be read or written unless otherwise specified . 5.1 registers table 5 - 2 shows the complete list of the ft81x r egisters. refer to ft81x _series_ programm er s _ guide , chapt er 2 for details of the register function . table 5 - 2 overview of ft81x registers address (hex) register name bit s r/ w reset value description 302 0 00 h reg_id 8 r/o 7c h identif i cation register, always reads as 7ch 3020 04 h reg_frames 32 r/o 0 frame counter, since reset 3020 08 h reg_clock 32 r/o 0 clock cycles, since reset 3020 0 c h reg_frequency 2 8 r/w 60000000 main clock f requency (hz) 3020 10 h reg_ rendermode 1 r/w 0 rendering mode: 0 = normal, 1 = single - line 3020 14 h reg_ snapy 11 r/w 0 scanline select for rendermode 1 3020 18 h reg_ snapshot 1 r/ w - trigger for rendermode 1 3020 1 ch reg_snap format 6 r/ w 20 h pixel format for scanline readout 3020 20 h reg_cpureset 3 r/w 2 graphics, audio and touch engines reset control . bit2: audio, bit1: touch, bit0: graphics 3020 2 4 h reg_tap_crc 32 r/o - live video tap crc . frame crc is
copyright ? 2015 future technology devices international limited 41 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 address (hex) register name bit s r/ w reset value description computed every dl swap . 3020 2 8 h reg_tap_mask 32 r/w ffffffff h live video tap mask 3020 2 c h reg_hcycle 12 r/w 224 h horizontal total cycle count 3020 30 h reg_hoffset 1 2 r/w 02b h horizontal display start o ff set 3020 3 4 h reg_hsize 1 2 r/w 1e0 h horizontal display pixel count 3020 3 8 h reg_hsync0 1 2 r/w 0 00h horizontal sync fall o ff set 3020 3 c h reg_hsync1 1 2 r/w 029 h horizontal sync rise o ff set 3020 40 h reg_vcycle 1 2 r/w 124 h vertical total cycle count 3020 4 4 h reg_voffset 1 2 r/w 00ch vertic al display start o ff set 3020 4 8 h reg_vsize 1 2 r/w 110 h vertical display line count 3020 4 c h reg_vsync0 10 r/w 0 00h vertical sync fall offset 3020 50 h reg_vsync1 10 r/w 00 a h vertical sync rise offset 3020 5 4 h reg_dlswap 2 r/ w 0 display list swap control 3020 5 8 h reg_rotate 3 r/w 0 screen rotat ion control. allow normal/ mirrored/inverted for landscape or portrait orientation . 3020 5 c h reg_outbits 9 r/w 1b6 h / 000h output bit resolution, 3 bits each for r/g/b. default is 6/6/6 bits for ft810/ft811, and 8/8/8 bits for ft812/ft813 (0b000
copyright ? 2015 future technology devices international limited 42 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 address (hex) register name bit s r/ w reset value description 3020 8 8 h reg_sound 16 r/w 0 so und effect select 3020 8 c h reg_play 1 r/ w 0h start e f fect playback 3020 90 h reg_gpio_dir 8 r/w 8 0 h legacy gpio pin direction, 0 = input , 1 = output 3020 9 4 h reg_gpio 8 r/ w 00h legacy gpio read/write 302098h reg_gpio x _dir 16 r/w 80 0 0 h extended gpio pin direction, 0 = input , 1 = output 3020 9 ch reg_gpio x 16 r/ w 00 80 h extended gpio read/write 3020 a0 h - 3020a4h reserved - - - reserved 3020 a8 h reg_int_flags 8 r/o 00h interrupt flags , clear by read 3020 a c h reg_int_en 1 r/w 0 global interrupt enable , 1=enable 3020 b 0 h reg_int_mask 8 r/w ff h individual i nterrupt enable , 1=enable 3020 b 4 h reg_playback_start 20 r /w 0 audio playback ram start address 3020 b 8 h reg_playback_length 20 r/w 0 audio playback sample length (bytes) 3020 b ch reg_playback_readptr 20 r/o - audio playback current read pointer 3020 c 0 h reg_playback_freq 16 r/w 8000 audio playback sampling frequency (hz) 3020 c 4 h reg_playback_format 2 r/w 0 audio playback format 3020 c 8 h reg_playback_loop 1 r/w 0 audio playback loop enable 3020 c ch reg_playback_play 1 r/ w 0 start audio playback 3020 d 0 h reg_pwm_hz 14 r/w 250 backlight pwm output frequency (hz) 3020 d 4 h reg_pwm_duty 8 r/w 128 backlight pwm output duty cycle 0=0%, 128=100% 3020 d 8 h reg_macro_0 32 r/w 0 display list macro command 0 3020 d ch reg_macro_1 32 r/w 0 display l ist macro command 1 3020 e 0 h C
copyright ? 2015 future technology devices international limited 43 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 address (hex) register name bit s r/ w reset value description 3020 fc h reg_cmd_write 12 r/ o 0 command buffer write pointer 302 100 h reg_cmd_dl 13 r/w 0 command dis play list offset 302 104 h reg_touch_mode 2 r/w 3 touch - screen sampling mode 302 108 h reg_touch_adc_mode reg_ c touch_ extended 1 r/w 1 set touch adc mode set capacitive touch operation mode: 0: extended mode (multi - touch) 1: ft800 compatibility mode (single touch) . 302 10c h reg_ touch_charge 16 r/w 9000 t ouch charge tim e, units of 6 clocks 302110h reg_ touch_settle 4 r/w 3 t ouch settl e time , units of 6 clocks 302114h reg_ touch_oversampl e 4 r/w 7 t ouch oversample factor 302118h reg_ touch_rzthresh 16 r/w ffffh touch resistance threshold 3021 1c h reg_touch_ raw_xy reg_ctouch_touch 1 _x y 32 r/o - compatibility mode: t ouch - screen raw (x - msb16 ; y - lsb16 ) extended mode: touch - screen screen data for touch 1 (x - msb1 6 ; y - lsb16 ) 3021 20 h reg_touch_rz reg_ c touch_ touch4_y 16 r/o - compatibility mode: t ouch - screen resistance extended mode: touch - screen screen y data for touch 4 3021 24 h reg_touch_ screen_xy reg_ctouch_touch 0 _x y 32 r/o - compatibility mode: t ouch - screen screen (x - msb16 ; y - lsb16 ) extended mode: touch - screen screen data for touch 0 (x - msb16 ; y - lsb16 ) 3021 28 h reg_touch_ tag_xy 32 r/o - touch - screen screen (x - msb16 ; y - lsb16 ) used for tag 0 lookup 3021 2c h reg_touch_tag 8 r/o - touch - screen ta g result 0 302130h reg_touch_ tag 1 _xy 32 r/o - touch - screen screen (x - msb16 ; y - lsb16 ) used for tag 1 lookup 302134h reg_touch_tag 1 8 r/o - touch - screen tag result 1 302138h reg_touch_ tag 2 _xy 32 r/o - touch - screen screen (x - msb16 ; y - lsb16 ) u sed for tag 2 lookup 30213ch reg_touch_tag 2 8 r/o - touch - screen tag result 2
copyright ? 2015 future technology devices international limited 44 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 address (hex) register name bit s r/ w reset value description 302140h reg_touch_ tag 3 _xy 32 r/o - touch - screen screen (x - msb16 ; y - lsb16 ) used for tag 3 lookup 302144h reg_touch_tag 3 8 r/o - touch - screen tag result 3 302148h reg_touch_ tag 4 _xy 32 r/o - touch - screen screen (x - msb16 ; y - lsb16 ) used for tag 4 lookup 30214ch reg_touch_tag 4 8 r/o - touch - screen tag result 4 3021 50 h reg_ touch_transform _a 32 r/w 000 10000 h touch - screen transform coefficient (s15.16) 3021 54 h reg_ touch_transform _b 32 r/w 0 0000000h touch - screen transform coefficient (s15.16) 3021 58 h reg_ touch_transform _c 32 r/w 0 0000000h touch - screen transform coeff i cient (s15.16) 3021 5c h reg_ touch_transform _d 32 r/w 0 0000000h touch - screen tran sform coefficient (s15.16) 3021 60 h reg_ touch_transform _e 32 r/w 000 10000 h touch - screen transform coefficient (s15.16) 3021 64 h reg_ touch_transform _f 32 r/w 0 0000000h touch - screen transform coefficient (s15.16) 3021 68 h reg_touch_config 16 r/w 8381h(ft8 10/ft812) 0381h(ft8 11/ft813) touch configuration. rtp/ctp select rtp: short - circuit, sample clocks ctp: i2c address, ctpm type, low - power mode 3021 6c h reg_ctouch_touch4_x 16 r/o - extended mode: touch - screen screen x data for touch 4 302170 h reserved - - - reserved 3021 74 h reg _ bist _ en 1 r/w 0 bist memory mapping enable
copyright ? 2015 future technology devices international limited 45 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 address (hex) register name bit s r/ w reset value description 30 2178h reserved - - - reserved 30217ch reserved - - - reserved 302180 h reg_trim 8 r/w 0 internal relaxation clock trimming 3021 84 h reg_ana_comp 8 r/w 0 analogue control register 3021 88 h reg_spi_width 3 r/w 0 qspi bus width setting bit [2]: extra dummy cycle on read bit [1:0]: bus width (0=1 - bit, 1=2 - bit, 2=4 - bit) 30218c h reg_touch_direct_xy reg_ctouch_touch 2 _x y 32 r/o - compatibility mode: touch screen direct (x - msb16 ; y - lsb16 ) conversions extended mode: touch - screen screen data for touch 2 (x - msb16 ; y - lsb16 ) 302190 h reg_touch_direct_z1z 2 reg_ctouch_touch 3 _x y 32 r/o - compatibility mode: touch screen direct (z1 - msb16; z2 - lsb16 ) conversions extende d mode: touch - screen screen data for touch 3 (x - msb16 ; y - lsb16 ) 302194h - 302560h reserved - - - reserved 302564 h reg_datestamp 128 r/o - stamp date code 302574h reg_cmdb_space 12 r/w ffch command dl (bulk) space available 30257 8 h reg_cmdb_write 32 w/o 0 command dl (bulk) write note: all register addresses are 4 - byte aligned. the value in the bits column refers to the number of valid bits from bit 0 unless otherwise specified; other bits are reserved. 5.2 chip id the ft81x chip id can be read at memory location 0c0000 h C 0c0003 h. the reset value s of these bytes are: - 0c0000 h: 08h - 0c0001 h: 10h (ft810), 11h(ft811), 12h(ft812), 13h(ft813) - 0c0002h: 01h - 0c0003h: 00h note that the chip id location can be over - writ t en by software .
copyright ? 2015 future technology devices international limited 46 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 6 devices characteristics and ratings 6.1 absolute maximum ratings the absolute maximum ratings for the ft81x device are as follows. these are in accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. table 6 - 1 absolute maximum ratings parameter value unit storage temperature - 65 to + 150 c floor life (out of bag) at factory ambient (30c / 60% relative humidity) 168 (ip c/jedec j - std - 033a msl level 3 compliant)* hours ambient temperature (power applied) - 40 to + 85 c vcc supply voltage 0 to + 4 v vccio supply voltage 0 to + 4 v dc input voltage - 0.5 to + ( vccio + 0.3 ) v * if the devices are stored out of the packaging , beyond this time limit , the devices should be baked before use. the devices should be ramped up to a temperature of +125c and baked for up to 17 hours. 6.2 esd and latch - up specifications table 6 - 2 esd and lat ch - up specifications description specification human body mode (hbm) > 2kv machine mode (mm) > 200v charged device mode (cdm) > 500v latch - up > 200ma 6.3 dc characteristics table 6 - 3 operating voltage and current parameter description minimum typical maximum units conditions vccio 1/ vccio2 vcc io o perating s upply v oltage 1.62 1.8 0 1.98 v normal operation 2.2 5 2.5 0 2.75 v 2.97 3.3 0 3.63 v vcc vcc o perating s upply v oltage 2.97 3.3 0 3.63 v normal operation
copyright ? 2015 future technology devices international limited 47 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 parameter description minimum typical maximum units conditions icc1 power down current - 0. 17 - ma power down mode icc 2 sleep current - 0.76 - ma sleep mode icc 3 standby current - 1.8 - ma standby mode icc 4 operating c urrent - 22 - ma normal operation table 6 - 4 digital i/o pin characteristics ( vcc io = +3.3v ) parameter description minimum typical maximum units conditions voh output voltage high vccio - 0.4 - - v ioh=5ma vol output voltage low - - 0.4 v iol=5ma vi h input high voltage 2.0 - - v v il input low voltage - - 0.8 v vth schmitt hysteresis voltage 0. 22 - 0. 3 v iin input leakage current - 10 - 10 ua vin = vccio or 0 ioz tri - state output leakage current - 10 - 10 ua vin = vccio or 0 rpu pull - up resistor - 42 - k? rp d pull - down resistor - 44 - k? table 6 - 5 digital i/o pin characteristics (vccio = +2.5v ) parameter description minimum typica l maximum units conditions voh output voltage high vccio - 0.4 - - v ioh= 5 ma vol output voltage low - - 0.4 v iol= 5 ma vih input high voltage 1.7 - - v - vil input low voltage - - 0.7 v - vth schmitt hysteresis voltage 0. 2 - 0 . 3 v - iin input leakage current - 10 - 10 ua vin = vccio or 0 ioz tri - state output leakage current - 10 - 10 ua vin = vccio or 0 rpu pull - up resistor - 57 - k?
copyright ? 2015 future technology devices international limited 48 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 rpd pull - down resistor - 59 - k? table 6 - 6 digital i/o pin characteristics (vccio = +1.8v ) parameter description minimum typical maximum units conditions voh output voltage high vccio - 0.4 - - v ioh= 5 ma vol output voltage low - - 0.4 v iol= 5 ma vih input high voltage 1.2 - - v - vil input low voltage - - 0.6 v - vth schmitt hysteresis voltage 0. 17 - 0. 3 v - iin input leakage current - 10 - 10 ua vin = vccio or 0 ioz tri - state output leakage current - 10 - 10 ua vin = vccio or 0 rpu pull - up resistor - 90 - k? rpd pull - down resistor - 97 - k? table 6 - 7 touch sense characteristics parameter description minimum typical maximum units conditions rsw - on x - ,x+,y - and y+ drive on resistance - 6 10 ? vccio=3.3v - 9 1 6 ? vccio=1.8v rsw - off x - ,x+,y - and y+ drive off resistance 10 - - m ? rpu touch sense pull up resistance 7 8 100 12 5 k ? vth+ touch detection rising - edge threshold on xp pin 1.59 - 2.04 v vccio=3.3v 0.58 - 0.68 v vccio=1.8v vth - touch detection falling - edge threshold on xp pin 1.23 - 1.55 v vccio=3.3v 0.51 - 0.56 v vccio=1.8v rl x - axis and y - axis drive load resistance 200 - - ?
copyright ? 2015 future technology devices international limited 49 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 6.4 ac characteristics 6.4.1 system clock and reset table 6 - 8 system clock characteristics parameter value unit s minimum typical maximum internal relaxation clock trimmed f requenc y - 12 - mhz frequency variation - 5 .5 - + 5 .5 % crystal f requency - 12.00 0 - mhz x1/x2 c apacitance - - 10 pf ext ernal clock input frequency - 12.00 0 - mhz d uty cycle 4 5 50 55 % input voltage on x1/clk - 3.3 - v reset reset pulse on pd_n 5 ms 6.4.2 spi interface timing figure 6 - 1 spi int erface timing
copyright ? 2015 future technology devices international limited 50 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 table 6 - 9 spi interface timing specification parameter description vcc i o =1.8v vcc i o =2.5v vcc i o =3.3v unit s min max min max min max tsclk spi clock period (single /dual mo de ) 33.3 33.3 33.3 ns tsclk spi clock period (quad mode) 40 40 40 ns tsclkl spi clock low duration 13 13 13 ns tsclkh spi clock high duration 13 13 13 ns tsac spi access time 4 3.5 3 ns ti su input setup 4 3.5 3 ns tih input hold 0 0 0 ns tzo output enable delay 16 13 11 ns toz output disable delay 13 11 10 ns tod output data delay 15 12 11 ns tcsnh csn hold time 0 0 0 ns 6.4.3 rgb interface t iming table 6 - 10 rgb interface timing characteristics parameter description value unit s min typ max tpclk pixel clock period 1 5 . 7 ns tpclkdc pixel clock d uty cycle 40 50 60 % td output delay relative to pclk rising edge (reg_pclk_pol=0) or falling edge (reg_pclk_pol=1). applied for all the rgb output pins. 4 ns t h output hold time relative to pclk rising edge (reg_pclk_pol=0) or falling edge (reg_pclk_pol=1) . applied for all the rgb output pins. 0.5 ns
copyright ? 2015 future technology devices international limited 51 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 6 - 2 r gb interface timing
copyright ? 2015 future technology devices international limited 52 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 7 application examples figure 7 - 1 ft812 application circuit figure 7 - 2 ft813 application circuit gnd b0 b1 b2 b3 b4 b5 b6 b7 r0 r1 r 2 r 3 r 4 r 5 r 6 r 7 g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 x p y p x m y m b l _ p w m pclk disp hsync vsync de gnd gnd y1 12mhz c8 18pf c7 18pf c1 4.7uf c6 0.1uf gnd c2 0.1uf d3v3 vout1v2 c4 0.1uf gnd d3v3 c3 0.1uf c5 0.1uf r2 r3 r4 r5 r6 r7 g2 g3 g4 g5 g6 g7 b2 b3 b4 b5 b6 b7 r1 33r r2 33r r3 33r r4 33r r5 33r r6 33r r7 33r r8 33r r9 33r r10 33r r11 33r r12 33r r14 33r r15 33r r16 33r r17 33r r18 33r r13 33r r19 33r r21 33r r22 33r r23 33r r20 33r r0 r1 g0 g1 b0 b1 r24 33r r25 33r r26 33r r27 33r r28 33r r29 33r pclk disp hsync vsync de ledk leda gnd d3v3 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 0 0 0 0 j1 0.5b-40pbs vled- vled+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 hsync vsync pclk disp nc vdd x1 y1 x2 de gnd gnd y2 r0 r1 r2 r3 r4 r5 r6 r7 g0 g1 g2 g3 g4 g5 g6 g7 b0 b1 b2 b3 b4 b5 b6 b7 gnd [left] [right] [bottom] [top] lcd1 ym xm yp xp aud_pwm spi_int# spi_pd# spi_io3 spi_io2 spi_cs# spi_miso spi_mosi qspi master aud_pd# spi_sck mcu audio_l 3 gnd 4 sck 5 miso/io1 6 mosi/io0 7 cs_n 8 gpio0/io2 9 gpio1/io3 10 vccio1 11 gpio2 12 int_n 13 pd_n 14 x 1 / c l k 1 6 x 2 1 7 g n d 1 8 v c c 1 9 v o u t 1 v 2 2 0 v c c 2 1 v c c i o 2 2 2 x p 2 3 y p 2 4 x m 2 5 y m 2 6 g n d 2 7 de 29 vsync 30 hsync 31 disp 32 pclk 33 b7 34 b6 35 b5 36 b4 37 b3 38 b2 39 gnd 42 g 7 4 3 g 6 4 4 g 5 4 5 g 4 4 6 g 3 4 7 g 2 4 8 r 7 5 1 r 6 5 2 r 5 5 3 r 4 5 4 r 3 5 5 r 2 5 6 g n d e p r1 1 r0 2 g p i o 3 1 5 b a c k l i g h t 2 8 b0 41 b1 40 g 1 4 9 g 0 5 0 u1 ic_ft812q gnd b0 b1 b2 b3 b4 b5 b6 b7 r0 r1 r 2 r 3 r 4 r 5 r 6 r 7 g 0 g 1 g 2 g 3 g 4 g 5 g 6 g 7 c t p _ r s t # c t p _ i n t # c t p _ s c l c t p _ s d a b l _ p w m pclk disp hsync vsync de gnd gnd y1 12mhz c8 18pf c7 18pf c1 4.7uf c6 0.1uf gnd c2 0.1uf d3v3 vout1v2 c4 0.1uf gnd d3v3 c3 0.1uf c5 0.1uf r2 r3 r4 r5 r6 r7 g2 g3 g4 g5 g6 g7 b2 b3 b4 b5 b6 b7 r1 33r r2 33r r3 33r r4 33r r5 33r r6 33r r7 33r r8 33r r9 33r r10 33r r11 33r r12 33r r14 33r r15 33r r16 33r r17 33r r18 33r r13 33r r19 33r r21 33r r22 33r r23 33r r20 33r r0 r1 g0 g1 b0 b1 r24 33r r25 33r r26 33r r27 33r r28 33r r29 33r pclk disp hsync vsync de ledk leda gnd d3v3 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 0 0 0 0 j1 0.5b-40pbs vled- vled+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 hsync vsync pclk disp nc vdd x1 y1 x2 de gnd gnd y2 r0 r1 r2 r3 r4 r5 r6 r7 g0 g1 g2 g3 g4 g5 g6 g7 b0 b1 b2 b3 b4 b5 b6 b7 gnd [left] [right] [bottom] [top] lcd1 aud_pwm spi_int# spi_pd# spi_io3 spi_io2 spi_cs# spi_miso spi_mosi qspi master aud_pd# spi_sck 1 1 2 2 3 3 4 4 5 5 6 6 0 0 0 0 j2 cn_6pin_fpc bottom gnd ctp_sda ctp_scl ctp_rst# ctp_int# d3v3 r32 1k r31 1k r30 4.7k mcu audio_l 3 gnd 4 sck 5 miso/io1 6 mosi/io0 7 cs_n 8 gpio0/io2 9 gpio1/io3 10 vccio1 11 gpio2 12 int_n 13 pd_n 14 x 1 / c l k 1 6 x 2 1 7 g n d 1 8 v c c 1 9 v o u t 1 v 2 2 0 v c c 2 1 v c c i o 2 2 2 c t p _ r s t _ n 2 3 c t p _ i n t _ n 2 4 c t p _ s c l 2 5 c t p _ s d a 2 6 g n d 2 7 de 29 vsync 30 hsync 31 disp 32 pclk 33 b7 34 b6 35 b5 36 b4 37 b3 38 b2 39 gnd 42 g 7 4 3 g 6 4 4 g 5 4 5 g 4 4 6 g 3 4 7 g 2 4 8 r 7 5 1 r 6 5 2 r 5 5 3 r 4 5 4 r 3 5 5 r 2 5 6 g n d e p r1 1 r0 2 g p i o 3 1 5 b a c k l i g h t 2 8 b0 41 b1 40 g 1 4 9 g 0 5 0 u1 ft813q
copyright ? 2015 future technology devices international limited 53 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 figure 7 - 3 backlight drive circuit figure 7 - 4 audio filter and amplifier circuit gnd c22 0.22uf r40 4.7k c16 2.2nf d1 1n4148 r44 10k c17 10uf c18 0.1uf r45 1r6 led current sense r45 iled=95/1.6 = 60ma ledk leda bl_pwm gnd gnd gnd gnd gnd l1 nr3015t220m vout 1 vin 2 fb 6 en 3 a g n d 4 sw 7 p g n d 8 e p 9 u3 mic2289 d5v aud_pwm shdn 1 bypass 2 in+ 3 in- 4 vo+ 5 vdd 6 gnd 7 vo- 8 gnd 9 u2 tpa6205a1 c19 1uf r41 10k/1% r36 10k/1% r42 20k/1% r37 20k/1% c20 0.47uf c21 0.22uf agnd r43 47k r33 1k c12 4.7nf r34 1k c13 4.7nf r35 1k c14 4.7nf agnd agnd agnd vdd_aud aud_pd# agnd sp- sp+ agnd c10 0.1uf vdd_aud c11 10nf c9 100uf agnd gnd fb1 600r/1a fb2 600r/1a agnd agnd c15 0.47uf d3v3 sp1 1w/8ohm
copyright ? 2015 future technology devices international limited 54 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 8 package parameters the ft81x is available in v qf n - 48 and vqfn - 56 package s . the package di mensions, markings and solder reflow profile for all packages are described in following sections . 8.1 v qf n - 48 package dimensions a a1 a3 b d e d2 e2 e l k min. 0.80 0.00 0.20 5.15 5.15 0.35 0.20 nom. 0.85 0.02 0.20 0.25 7.00 7.00 5.20 5.2 0 0.50 0.40 max. 0.90 0.05 0.30 5.25 5.25 0.45 all dimensions are in millimetres (mm) figure 8 - 1 v qf n - 48 package dimensions 8.2 v qf n - 56 package di mensions a a1 a3 b d e d2 e2 e l k min. 0.80 0.00 0.20 5.85 5.85 0.30 0.20 nom. 0.85 0.02 0.20 0.25 8.00 8.00 5.90 5.90 0.50 0.40 max. 0.90 0.05 0.30 5.95 5.95 0.50 all dimensions are in millimetres (mm) figure 8 - 2 vqfn - 56 package dimensions
copyright ? 2015 future technology devices international limited 55 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 8.3 solder reflow profile the ft81x is supplied in a pb free vqfn - 48 or vqfn - 56 package. the recommended solder reflow profile for the pa ckage is shown in figure 8 - 3 . figure 8 - 3 ft81 x solder reflow profile the recommended values for the solder reflow profile are detailed in table 8 - 1 . values are shown for both a completely pb free solder process (i.e. the ft81x is used with pb fr ee solder), and for a non - pb free solder process (i.e. the ft81x is used with non - pb free solder). table 8 - 1 reflow profile parameter values profile featu re pb free solder process non - pb free solder process average ramp up rate (t s to t p ) 3c / second max. 3c / second max. preheat - temperature min (t s min.) - temperature max (t s max.) - time (t s min to t s max) 150c 200c 60 to 12 0 seconds 100 c 150c 60 to 120 seconds time maintained above critical temperature t l : - temperature (t l ) - time (t l ) 217c 60 to 150 seconds 183c 60 to 150 seconds peak temperature (t p ) 260c 240c time within 5c of actual peak temperature (t p ) 20 to 40 seconds 2 0 to 4 0 seconds ramp down rate 6c / second max. 6c / second max. time for t= 25c to peak temperature, t p 8 minutes max. 6 minutes max. critical zone: when t is in the range t to t t e m p e r a t u r e , t ( d e g r e e s c ) time, t (seconds) 25 p t = 25 o c to t t p t p t l t preheat s t l ramp up l p ramp down t max s t min s
copyright ? 2015 future technology devices international limited 56 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 9 contact information head office C glasgow, uk unit 1, 2 seaward place, centurion business park glasgow g41 1hh united kingdom tel: +44 (0) 141 429 2777 fax: +44 (0) 141 429 2758 e - mail (sales) sales 1 @ftdichip.com e - mail (support) support 1 @ftdichip.com e - mail (general enquiries) admin1@ftdichip.com branch office C taipei, taiwan 2f, no. 516, sec. 1, neihu road taipei 114 taiwan, r.o.c. tel: +886 (0) 2 8797 1330 fax: +886 (0) 2 8751 9737 e - mail (sales) tw.sales1@ftdichip.com e - mail (support) tw.support1@ftdichip.com e - mail (general enquiries) tw.admin1@ftdichip.com branch office C tigard , oregon, usa 7130 sw fir loop tigard , or 97223 usa tel: +1 (503) 547 0988 fax: +1 (503) 547 0987 e - mail (sales) us.sales@ftdichip.com e - mail (support) us.support@ftdichip.com e - mail (general enquiries) us.admin@ftdichip.com branch office C shanghai, china room 1103 , no. 666 west huai h ai road, changn ing district shanghai, 200052 china tel: +86 21 62351596 fax: +86 21 62351595 e - mail (sales) cn.sales@ftdichip.com e - mail (support) cn.support@ftdichip.com e - mail (general enquiries) cn.admin@ftdichip.com web site http://www.ftdichip.com distributor and sales representatives please visit the sales network page of the ftdi web site for the con tact details of our distributor(s) and sales representative(s) in your country. system and equipment manufacturers and designers are responsible to ensure that their systems, and any future technology devices international ltd (ftdi) devices incorporated in th eir systems, meet all applicable safety, regulatory and system - level performance requirements. all application - related information in this document (including application descriptions, suggested ftdi devices and other materials) is provided for reference o nly. while ftdi has taken care to assure it is accurate, this information is subject to customer confirmation, and ftdi disclaims all liability for system designs and for any applications assistance provided by ftdi. use of ftdi devices in life support and /or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold harmless ftdi from any and all damages, claims, suits or expense resulting from such use. this document is subject to change without notice. no freedo m to use patents or other intellectual property rights is implied by the publication of this document. neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material o r electronic form without the prior written consent of the copyright holder. future technology devices international ltd, unit 1, 2 seaward place, centurion business park, glasgow g41 1hh, united kingdom. scotland registered company number: sc136640
copyright ? 2015 future technology devices international limited 57 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 appendix a C references useful application notes ft81x_series _ programmer _ guide an_252 ft800 audio primer an_254 ft800 designs with visual tft an_259 ft800 example with 8 - bit mcu an_275 ft800 example with arduino an_276 audio file conversion an_277 ft800 create user defined font an_291 ft800 create multi - language font an_299 ft800 ft801 internal clock trimming an_303 - ft800 image file conversion an_308 ft800 example with an 8 - bit mcu an_312 ft800 example with arm an_314 ft800 advanced techniques - working with bitmaps an_318 arduino library for ft800 series an_320 ft800 example with pic an_327 eve screen editor installation guide an_281 ft800 emulator library user guide an_333 ft800 and ft801 touch capabilities an_336 ft800 - selecting an lcd display ft800 series sample application eve frequently asked questions
copyright ? 2015 future technology devices international limited 58 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 appendix b - list of f igures and tables list of figures figure 2 - 1 ft81x block diagram ................................ ................................ ................................ ..... 4 figure 2 - 2 ft81x system design diagram ................................ ................................ ....................... 4 figure 4 - 1 spi master and slave in the master read case ................................ ................................ . 14 figure 4 - 2 single/dual spi interface connection ................................ ................................ ............. 14 figure 4 - 3 quad spi interface connection ................................ ................................ ...................... 15 figure 4 - 4 internal relaxation oscillator connection ................................ ................................ ......... 21 figure 4 - 5 crystal oscillator connection ................................ ................................ ......................... 21 figure 4 - 6 external clock input ................................ ................................ ................................ ..... 21 figure 4 - 7 rgb timing waveforms ................................ ................................ ................................ . 28 figure 4 - 8 resistive touch screen connection ................................ ................................ ................. 32 figure 4 - 9 touch screen connection ................................ ................................ .............................. 34 figure 4 - 10 internal regulator ................................ ................................ ................................ ...... 36 figure 4 - 11 power state transition ................................ ................................ ............................... 37 figure 6 - 1 spi interface timing ................................ ................................ ................................ .... 49 figure 6 - 2 rgb interface timing ................................ ................................ ................................ ... 51 figure 7 - 1 ft812 application circuit ................................ ................................ ............................... 52 figure 7 - 2 ft813 application circuit ................................ ................................ ............................... 52 figure 7 - 3 backlight drive circuit ................................ ................................ ................................ .. 53 figure 7 - 4 audio filter and amplifier circuit ................................ ................................ ..................... 53 figure 8 - 1 vqfn - 48 package dimensions ................................ ................................ ...................... 54 figure 8 - 2 vqfn - 56 package dimensions ................................ ................................ ...................... 54 figure 8 - 3 ft81x solder reflow profile ................................ ................................ .......................... 55 list of tables table 3 - 1 ft81x pin descript ion ................................ ................................ ................................ ...... 9 table 4 - 1 qspi channel selection ................................ ................................ ................................ .. 13 table 4 - 2 host memory read transaction ................................ ................................ ....................... 15 table 4 - 3 host memory write transaction ................................ ................................ ...................... 16 table 4 - 4 host command transaction ................................ ................................ ............................ 16 table 4 - 5 host command list ................................ ................................ ................................ ........ 16 table 4 - 6 interrupt flags bit assignment ................................ ................................ ....................... 20 table 4 - 7 font table format ................................ ................................ ................................ ......... 23 table 4 - 8 rom font table ................................ ................................ ................................ ............. 23 table 4 - 9 rom font ascii character width in pixels ................................ ................................ ......... 23 table 4 - 10 rom font extended as cii characters ................................ ................................ ............ 25 table 4 - 11 rgb pclk frequency ................................ ................................ ................................ ... 26 table 4 - 12 reg_swizzle rgb pins mapping ................................ ................................ ................. 27 table 4 - 13 registers for rgb horizontal and vertical timings ................................ ............................ 27 table 4 - 14 output drive current selection ................................ ................................ ...................... 29
copyright ? 2015 future technology devices international limited 59 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 table 4 - 15 sound effect ................................ ................................ ................................ .............. 30 table 4 - 16 midi note effect ................................ ................................ ................................ ......... 31 table 4 - 17 resistive touch controller operating mode ................................ ................................ .... 33 table 4 - 18 capacitive touch controller operating mode ................................ ................................ .. 34 table 4 - 19 power supply ................................ ................................ ................................ ............. 36 table 4 - 20 pin status ................................ ................................ ................................ .................. 38 table 5 - 1 ft81x memory map ................................ ................................ ................................ ...... 40 table 5 - 2 overview of ft81x registers ................................ ................................ .......................... 40 table 6 - 1 absolute maximum ratings ................................ ................................ ............................ 46 table 6 - 2 esd and latch - up specifications ................................ ................................ .................... 46 table 6 - 3 operating voltage and current ................................ ................................ ....................... 46 table 6 - 4 digital i/o pin characteristics (vccio = +3.3v) ................................ ............................... 47 table 6 - 5 digital i/ o pin characteristics (vccio = +2.5v) ................................ ............................... 47 table 6 - 6 digital i/o pin characteristics (vccio = +1.8v) ................................ ............................... 48 table 6 - 7 touch sense char acteristics ................................ ................................ .......................... 48 table 6 - 8 system clock characteristics ................................ ................................ .......................... 49 table 6 - 9 spi interface timing specification ................................ ................................ .................. 50 table 6 - 10 rgb interface timing characteristics ................................ ................................ .............. 50 table 8 - 1 reflow profile parameter values ................................ ................................ ..................... 55
copyright ? 2015 future technology devices international limited 60 document no.: ft_001165 ft81x embedded video engine datasheet version 1.2 clearance no.: ftdi#440 appendix c - re vision history document title: ft81x embedded video engine datasheet document reference no.: ft_ 001165 clearance no.: ftdi#440 product page: http://www.ftdichip.com/ eve .htm document feedback: ds_ ft81x revision changes date draft initial release 2015 - 0 2 - 1 5 1.0 revised release 2015 - 07 - 07 1.1 revised release 2015 - 09 - 14 1.2 revised release 2015 - 09 - 29

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